הטכניון מכון טכנולוגי לישראלXyz
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים 
Ph.D and MS.c Theses, since 1988.


Advisor Professor Ran Ginosar
Advisor's Email ran@ee.technion.ac.il
Advisor's Home-Site www
No of theses 66
Department Electrical Engineering
Department Web Site webee.technion.ac.il/hebrew


No.   Student's Name Graduation
Year
Degree Abstracts Research Name
 1 Kaplan Roman 2020 PhD Abstracts In-Memory Accelerator Architectures for Bioinformatics and Machine Learning
 2 Azriel Leonid 2020 PhD Abstracts From Device Level to Systems - Advance Topics in Hardware Security
 3 Yankilevich Yevgeny 2018 MSc Abstracts Fast and Efficient Soft Errors Detection and Correction in CAM and TCAM
 4 Ramadan Misbah 2017 MSc Abstracts Adaptive Programming for Multi-Level Cell ReRAM
 5 Kaplan Roman 2016 MSc Abstracts Accelerating SpMV Multiplication using Compression on the Plural Many-Core Architecture
 6 Morad Amir 2016 PhD Abstracts Multicore and Processing-in-Memory Architectures
 7 Diamant Ron 2015 MSc Abstracts Asynchronous Sub-threshold Ultra-low Power Processor
 8 Nassar Mohammad 2015 MSc Abstracts Many-Core Architecture
 9 Zhang Yongxin 2015 MSc Abstracts High Speed Receiver Circuit for On-Chip Communications
 10 Rotem Efraim 2015 PhD Abstracts High Performance Computing in Physically Constrained Environment
 11 Yavits Leonid 2015 PhD Abstracts Analysis and Optimization of Parallel Computing Architectures and in-Memory Computing
 12 Beer Gingold Salomon Michel 2014 PhD Abstracts Metastability and Synchronization in VLSI systems
 13 Adato Avi 2013 MSc Abstracts Design Methods to Reduce Radiation Effects on Electronic Circuits
 14 Manor Shimon 2013 MSc Abstracts Multi-Synchronous Clocking for Low Power
 15 Nahmanny Danniel 2013 MSc Abstracts High-Speed, Currnet-Mode, Serial Link Communication
 16 Naveh Alon 2013 MSc Abstracts Power Aware Scheduling in a Heterogeneous Processor
 17 Verbitsky Dmitry 2013 MSc Abstracts Automatic Recognition and Verification of Handshake-Based Synchronizers
 18 Jacob Prarthana 2013 MSc Abstracts Testing of a Fast on Chip Serial Link
 19 Avron Itai 2012 MSc Abstracts Scheduler Performance in Many-core Architecture
 20 Nave Eyal-Itzhak 2012 MSc Abstracts TCP Window Based Dynamic Voltage and Frequency Scaling (DVFS) for Low Power Communication Network Controller System on Chip (SoC)
 21 Cohen Yaron 2012 MSc Abstracts Low Power D/A Converter Design Considerations
 22 Abdelhadi Ameer 2011 MSc Abstracts Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks
 23 Friedman Eyal 2011 MSc Abstracts Processor-to-Memory Non-Equidistant Network in a Many-Core Architecture
 24 Khoretz Dmitri 2011 MSc Abstracts Cores and Memory Performance of HyperCorex: Many-Core Architecture
 25 Vainbrand Dmitri 2010 MSc Abstracts Network-on-Chip Architecture for Neural Networks
 26 Vaisband Inna 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction
 27 Dobkin Rostislav 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC
 28 Baron Asaf 2008 MSc Abstracts The Capacity Allocation Paradox
 29 Morgenshtein Arkadiy 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect
 30 Elyada Avshalom 2007 MSc Abstracts Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors
 31 Yekutieli Ziv 2007 MSc Abstracts Integrated Multi-Electrode Array: An Interface to Ex Vivo Neural Networks
 32 Kayam Michael 2007 MSc Abstracts Synchronizers for Low Voltage and Low temerature Operation
 33 Tolchinsky Michael 2007 MSc Abstracts Implementation of New Method of Measurement for Metastability Coefficient for Flip-flops
 34 Perelman Yevgeny 2007 PhD Abstracts The Neuroprocessor: An Integrated Interface to Biological Neural Networks
 35 Bolotin Evgeny 2007 PhD Abstracts Network on Chip
 36 Walter Isask'har 2006 MSc Abstracts Quality of Service in Network on-Chip
 37 Kapschitz Yitschak 2006 MSc Abstracts Formal verification of synchronizers
 38 Lyakhov Alexander 2006 MSc
VLSI Sensor Chip for In-Vitro Measurement of Biological Neural Network Activity
 39 Obridko Ilya 2005 MSc Abstracts Minimal Energy Asynchronous Adder Architectures
 40 Zviagintsev Alex 2005 MSc Abstracts Hardware Algorithms and Architectures for Power Spike Detection and Sorting
 41 Frank Uri 2005 MSc Abstracts A Predictive Synchronizer for Bridging Different Frequency Clock Domains
 42 Tamir Guy 2004 MSc Abstracts Synchronizers Metastability
 43 Semiat Yaron 2003 MSc Abstracts Design, Implementation and Test of Adaptive Synchronization Circuits
 44 Katz Sagi 2003 MSc Abstracts Polyhedral Surface Decomposition and Applications
 45 Dobkin Rostislav 2003 MSc Abstracts Parallel VLSI Architecture and Parallel Interleaver Design for MAP Turbo Decoder
 46 Elboim Yaron 2002 MSc
A Clock Tuning Circuit for System-on-Chip
 47 Perelman Yevgeny 2001 MSc
A Low-Light Sensor for Medical Diagnostic Applications
 48 Shpolyansky Boris 1999 MSc
Improving of Performance of Superscalar Microprocessors Using Scheduling History
 49 Kol Rakefet 1998 PhD
Self-Timed Asynchronous Architecture of an Advanced General Purpose Microprocessor
 50 Finkelstein Hod 1998 MSc
Frontside-Bombarded Metal-Plated Electron Radiation Imaging Chip Fabricated in Cmos Technology
 51 Sherman Marina 1997 MSc
Intelligent-Scan Based Transmission and Retrieval of Images
 52 Chen-Levy Sarit 1995 MSc
Adaptive Sensitivity Ccd Image Sensor
 53 Freizeit Amir 1995 MSc
Hierarchical Conditional Replenishment Video Compression Algorithm and Architecture
 54 Yavits Leonid 1995 MSc
Architecture and Design of An Associative Processor Chip
 55 Weinberg Nitzan 1995 MSc
A Neural Network Architecture for Image Processing
 56 Harsat Arie 1993 PhD
Llsi Architectures for Flat Concurrent Prolog
 57 Wolf Stuart 1992 MSc
Development of a Colour Enhancealgorithm Using Spatial Proce
 58 Gur Shimon 1990 MSc
Design of Carmel 2 and Its Implementation with Silicon
 59 Yadid-Pecht Orly 1990 MSc
An Lmaging System with Random Access
 60 Alon Dov 1989 MSc
Switch Controller for Mp/l Parallel Processor
 61 Friedlander Baruch-Ram 1989 MSc
Vlsi Architecture for Morphological Operations
 62 Mintz Aviad 1989 MSc
Design of Vlsi Prolessor for Hough Transform
 63 Nathan Abraham 1989 MSc
Compilation of Fcp to Carmel and Its Performance Analysis
 64 Rotman Alan 1989 MSc
Control Unit Syntesis from a High Level Language
 65 Kol Rakefet 1989 MSc
Self-Timed Finite-State Machines
 66 Telichevesky Ricardo 1988 MSc
A Vlsi Architecture for Fntelligent Scan Image Processing

Last updated on: Monday ,September 7, 2020