|M.Sc Student||Dahan Mor Mordechai|
|Subject||C-AND: Mixed Writing Scheme for Disturb|
Reduction in 1T Ferroelectric FET Memory
|Department||Department of Electrical and Computer Engineering||Supervisor||ASSOCIATE PROF. Shahar Kvatinsky|
|Full Thesis text|
Ferroelectricity is a characteristic of materials that exhibit spontaneous electric polarization (built-in dipoles). These materials usually exhibit two stable saturated polarization states, pointing in opposite directions. To switch between the states, an external electric field must be applied.
A Ferroelectric Field Effect Transistor (FeFET) is a four-terminal device (Gate, Source, Drain, and Bulk) that features a ferroelectric layer instead of (or in addition to) the standard dielectric layer in the gate stack. Considering the two polarization states of the ferroelectric layer, the FeFET either displays a low threshold voltage (programmed state, logic ‘1’) or a high threshold voltage (erased state, logic ‘0’). By applying a sufficiently high external voltage along the ferroelectric layer (gate-bulk voltage), the polarization can be reversed, thereby changing the conductivity of the transistor channel. In this manner, the threshold voltage of the transistor can be actively manipulated. The FeFET usually displays asymmetric switching voltages.
FeFET memory has shown the potential to meet the requirements of the growing need for fast, dense, low-power, and non-volatile memories. Previously a single FeFET (1FeFET) memory cell was presented, named AND. Yet, the AND array configuration suffers from potential disturbs of surrounding cells during the read and write operations of a specific cell. During a write operation, the usage of the VDD/3 write scheme can cause to write disturb of unselected cells, due to the asymmetric switching voltages. Also, during a read operation, leakage currents of unselected devices are summed up, preventing sensing a current of a single device and can therefore cause read errors.
This dissertation proposes a memory architecture named crossed-AND (C-AND). The C AND architecture exploits the FeFET features to design a novel memory array structure based on a single FeFET in each memory cell. For the write operation, we propose a write scheme that addresses the potentially asymmetric switching voltage of the FeFET by combining the VDD/3 and VDD/2 write schemes to utilize different absolute write voltages. With that technique, we prevent the application of inversed polarity voltages that can cause unwanted writes to unselected cells. The C-AND architecture lowers the leakage currents and enables the usage of BLs with more cells compared to the AND architecture. Thanks to that, the read errors that can occur in the AND architecture are reduced with the C-AND architecture. Additionally, the suggested C AND architecture reduces the cell area by up to 2.92X compared to the AND architecture.
FeFET devices can be used not only for memory applications but also for computation. We present as future work the ability to execute logic operation within the suggested C AND memory architecture and use the memory array also as Content Addressable Memory (CAM). Ongoing research is aiming to implement a Binary Neural Network (BNN) accelerator using Computing In Memory (CIM) with the proposed C-AND architecture.