טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentGutkin Yakov
SubjectA Multi-Octave Microwave 6 Bit True Time Delay (TTD)
DepartmentDepartment of Electrical Engineering
Supervisor Dr. Emmanuel Cohen
Full Thesis textFull thesis text - English Version


Abstract

Some microwave systems utilize true time delay (TTD) components (rather than a phase shifter). A typical example is a phased array antenna for wideband applications. Phase array systems, in radar and other RF applications, allow significant increase of effective radiated power and RF range linking by taking advantage of spatial directivity. Active phased array antennas are presently used for both radar and electronic military functions and therefore require a wideband behavior. Since the advanced systems based on phased array may contain hundreds of transmit/receive modules, antenna size, weight and cost are very critical. Phase shifters are usually used for narrowband applications, but we can’t use them for wideband applications, because of beam squinting on the radar’s performance.  For a large phased array with many radiating elements many such components are needed. Phase array antenna is used to electronically direct the transmission beam. In radar applications, TTD is critical for wideband system because there is invariance of time delay with phase and frequency.

To obtain small size and low cost the TTD elements must be implemented as silicon chips using monolithic technology. In this research we describe the design, layout and performance of a 6-bit TTD chip operating over the entire band of 2-18GHz. The chip is implemented in TSMC 65nm technology. The covered range is 64ps and least significant bit is 1ps. The design is based on the concept of an all pass network with some modifications intended to reduce the number of unit cells. Thus, the first three bits are implemented in a single delay cell. Each one of bit4 and bit5 are implemented as single all pass network unit and a peaking buffer amplifier between them is used to improve impedance matching and partial compensation of the insertion loss slope of the whole chain. Bit6 is implemented using two all pass network units.

The physical size of the complete chip is 1.15mm2 which is acceptable, passive component - no power consumption, the maximum rms delay error is 1psec over most of the band and all 64 states. The input and output return loss are more than 10db over the entire band and all 64 states. The insertion loss is between 2.5-6db over the entire band and all 64 states which is much better than other SOA publications.