M.Sc Thesis

M.Sc StudentRecher Dan
SubjectuVP: Efficient Implementation of Value Prediction via
Micro-Op Cache
DepartmentDepartment of Electrical and Computers Engineering
Supervisor PROF. Avi Mendelson
Full Thesis textFull thesis text - English Version


The use of VP (Value Prediction) has already shown its potential benefit in enhancing the performance of OOO (Out-Of-Order) processor architectures in many studies. Thus, its complexity and additional power consumption prevent implementing it as part of current processors. In this work, we present the uVP method that aims to predict the value of operations while still preserving the internal micro-architectural features like Micro-op operations in general and in particular with the Micro-op cache. This method provides the most potential benefit of using value prediction, with manageable power, area, and complexity overhead.

This work suggests allowing value prediction to be integrated as part of the Micro-op cache without significant changes so it can leverage its power and performance benefits without disrupting the performance advantage of value prediction; it describes the new mechanism, discussed its characteristics, and compares it with a simple value prediction mechanism, named LVP (last value prediction) and state-of-the-art mechanisms, such as VTAGE which uses context-based methods like using global branch history. We will show that the new proposed novel integration enables an efficient implementation of value prediction without any significant performance loss in comparison with existing VP implementation by implementing it in the Sniper simulator and running SPEC2017 benchmarks.