|Ph.D Student||Sheleg Gil|
|Subject||Planar and Vertical Transistors based on Hybrid Organic|
and Metal Oxide Semiconductor Materials
|Department||Department of Electrical and Computer Engineering||Supervisor||PROF. Nir Tessler|
In recent years researchers have invested much of their time and effort to lower the cost of standard amorphous Si-based (α-Si) Thin-Film Transistors (TFTs) technology by investigating new semiconductor materials and devices architectures. Organic and metal oxide semiconductor materials gained a great deal of attention in that respect. Organic and Metal-Oxide-based Field Effect Transistors (OFETs/ MOTFTs) can introduce capabilities like flexibility, transparency, and ease of production to the pool of microelectronics and nanoelectronics, making them appealing to some applications. However, organics fall short in performance concerning the industry-standard α-Si TFT. The carbon-based π-conjugated organic materials suffer from low mobility due to their disorder nature. Shortening the channel length may bridge the gap of the organic materials' low mobility; however, lithography processes have to be used to achieve it. Since lithography is well developed for inorganic materials but not for organic materials, it adds another level of complexity that discourages its implementation instead of Si-based devices. For metal oxides semiconductor, mobility is in pair with α-Si base technology, but it suffers from device degradation over time due to its interface chemical interaction. Scientists use different passivation layers to suppress the metal oxide degradation, but short channel effects and injection mechanisms to the metal oxides are still an issue for those materials. Therefore, it is possible to implement them in insensitive applications like active-matrix organic light-emitting diode displays as the current driving elements, but it serves as a niche market.
Vertical Field Effect Transistors (VFETs) architecture is one of the options to overcome the inherent disadvantages. VFETs are made of three terminals: source, drain, and gate, similar to the traditional TFTs. The difference between VFET and TFT architectures is the location of the drain contact with respect to the source contact. In the vertical architecture, the contacts are sandwiched on top of each other with a semiconductor material in between. Conversely, in a traditional planar transistor, the contacts are on the same plane, one next to the other, with a semiconductor in the middle. The unique vertical architecture promotes low-cost design to realize short channel transistors, improving the device performance with minimal added cost.
This work addresses specific downfalls in the vertical architecture to investigate and improve the device's electrical performance. We have combined computer-aided design 2D simulation with device fabrication to study the device performance changes. First, we have focused our attention on the absence of saturation in vertical architecture and the short channel effect arising from the shortening of the device dimensions. After that, we invented a simple injecting electrode type that improves the short channel effects present in low mobility short channel vertical and planar transistors.
In addition to the simulation and experimental work, we worked sequentially to tie the simulation knowledge to the experimental outcome. We invested many resources to develop a one-of-a-kind source contact; therefore, we gained a profound understanding of different fabrication techniques. In some cases, we had to do failure evaluations to understand why the fabrication process failed to give the intended results.