|M.Sc Student||Melamed Itamar|
|Subject||LO Generation Based PLL for Millimeter Wave Phased-Arrays|
|Department||Department of Electrical Engineering||Supervisor||Dr. Emmanuel Cohen|
|Full Thesis text|
The demand for high data rate wireless links supporting 5G communication standards while providing a low power consumption for mobile devices requires new
architectures in circuit design. Recent advances in silicon technology have made
possible the realization of phased-arrays radios that are low in cost and small in size.
These phased-arrays are required in order to compensate for high free-space-path-
loss at mm-wave frequencies and utilize a higher gain from the antenna. For phased-
arrays, at the transmitter side, there is a N2 increase in the effective-radiated-power, and a N increased power in the receive side as compared to a single radiating element, which leads to a significant improvement in RF (Radio-Frequency) link quality. The implementation of mm-wave phased-array systems that are low power and integrated into a standard CMOS process are not fully viable in current design approaches since in the different used architectures for phased-array there are power-inefficient components that need to be multiplied by the number of elements N, and increasing the total power consumption of the system significantly. In RF and LO (Local-Oscillator) phase-shifting architectures, both use high-frequency phase shifters that have a significant insertion loss, which needs to be compensated by a sufficient driving power. The digital phase-shifting approach that uses digital-to-analog converters (DAC) and combines both data modulation and phase shifting at the same time, also known to have low power efficiency. Moreover, in the digital phase-shifting and LO phase shifting, there is a significant problem of LO distribution over the die, which also introduces losses. In this work, we introduce a low power phase-locked loop (PLL), which is used for both LO generation and phase shift operation. This low power PLL will be placed in each transmitting element. In this way, phase-shifting operates in low frequencies, which reduces power consumption, and the LO distribution is reduced to a reference distribution, which operates at low frequencies and much easier to split and route. Since phase-shifting controls the LO signal, it is not required to have a large bandwidth as needed in the RF path, which reduce design complexity. Using a Sub-Sampling PLL, power consumption is reduced, and this approach is easily scalable for a large number of elements without LO routing complexity and power losses. A 10bit of phase-shifting divided into a coarse 4bit, and a fine 6bit is implemented with two different methods. By dividing the phase shift into two methods, the tight timing requirements for phase shifting mm-wave signals are significantly relaxed, which leads a simple design with low power consumption, and easily scalable to large arrays. The designed PLL manufactured in a standard TSMC 65nm process, operating in the range of 31.5-34.5GHz, and achieves 0.95° degree of integrated phase noise, resulting in approximately 1° resolution of phase shifting, while consuming only 4.2mW from 1.2 V power supply. Finally, this design is integrated into a 28GHz four-element phased-array transmitter.