M.Sc Thesis

M.Sc StudentGharaba Duha
SubjectMM-Wave Mixer First Receiver for Ultra Low Power
Phased Array Systems
DepartmentDepartment of Electrical and Computer Engineering
Supervisor ASSOCIATE PROF. Emmanuel Cohen
Full Thesis textFull thesis text - English Version


This work presents an ultra-low-power and low noise mixer-first IQ receiver front end at 60GHz. The proposed receiver architecture is designed and fabricated in the TSMC 28nm HPC process.

The critical blocks of the receiver front-end are low noise amplifiers (LNA) and mixers. LNA in general can consume high DC power, and power consumption is of great importance in MIMO transceivers systems. It’s hard to match LNA for maximum gain and minimum noise contribution simultaneously. Due to these issues with LNA, mixer first receivers have been developed, eliminating the need for LNA, with mixers that can achieve a good noise and gain performance and low power consumption without LNA.

IQ receiver architecture is used to reject the image frequency. The proposed IQ mixer-first receiver consists of two differential mixer stages in which transistors are biased at the strongly nonlinear subthreshold region to achieve high conversion gain with very low DC power consumption, and mixing is generated mainly due to drain current 2nd order nonlinearity, 180° hybrid for differential LO signals, quadrature hybrid for 90° shift between LO signals of I and Q stages, and two base-band amplifiers each one converts the differential outputs of the mixers to single-ended output. Receiver architecture in this work is targeted for low LO to RF leakage, and low LO power drive.

The receiver system has been studied theoretically and simulated by advanced EM simulation tools. Full chip EM simulation shows 7.7dB NF and 23.9dB voltage conversion gain at IF frequency 1GHz for RF drive power of -40dbm at 60GHz, and LO power drive of -7dbm at 59GHz. LO-to-RF leakage power is -45.6dbm, -7dbm LO power drive found to be the optimal value for lower NF and higher Gain. 

The receiver test chip is measured on an un-bumped wafer on Pico-probe station with equipment that suits 60GHz circuits. The measured NF is 10.2dB, conversion gain is 20.4dB at 1GHz IF frequency, and LO-to-RF leakage power is -40.2dbm for RF drive power of -40dbm at 60GHz and LO drive power of -7dbm at 59GHz.

The EM simulated results show some discrepancies comparing to schematic design performance due to on-chip components parasitic effects, the difficulty of designing a very symmetric receiver layout, and the sensitivity of this architecture to variations in capacitors' values. Measured results have a good correlation with the full EM simulation results, inaccuracies of the measurement lab instruments can generate 2-3dB degradation in measured NF and gain comparing to EM simulated values.

 The receiver consumes 2mW and occupies a 0.05mm? active area. The small size and low power consumption make this design a good candidate for large array integration systems for 5G applications.