|Ph.D Student||Danial Loai|
|Subject||Neuromorphic Data Converters using|
|Department||Department of Electrical and Computer Engineering||Supervisor||ASSOCIATE PROF. Shahar Kvatinsky|
|Full Thesis text|
Data converters are ubiquitous in mixed-signal electronic systems, becoming the computational bottleneck in traditional data acquisition and emerging brain-inspired neuromorphic systems which aim to accelerate artificial intelligence algorithms. Unfortunately, conventional Nyquist data converters trade off speed, power, and accuracy. Therefore, they are exhaustively customized for special purpose applications. Furthermore, intrinsic real-time and post-silicon variations dramatically degrade their performance along with the CMOS technology downscaling.
This thesis presents novel neuromorphic analog-to-digital converters (ADC) and digital-to-analog (DAC) converters that are trained using the stochastic gradient descent algorithm to autonomously adapt to different design specifications, including multiple full-scale voltages, number of resolution bits, and sampling frequencies. We experimentally demonstrate the feasibility of the neuromorphic paradigm using commercial integrated memory arrays, comprising two-terminal floating-gate memristive devices fabricated in the standard 180nm CMOS process and operate at the low-power sub-threshold mode. This memristive array efficiently implements multiply, accumulate, and update operations essential for trainable artificial synapses in neuromorphic systems, at the analog level. Theoretical analysis, as well as simulation results, show the collective resilient properties of our converters in application reconfiguration, mismatches calibration, noise tolerance, and power optimization. We believe that our findings will spur the development of very large-scale integrated memristive neuromorphic systems with training capabilities.