|M.Sc Student||Sarfati Eyal|
|Subject||VLSI Delay Tuning by Signal Shielding|
|Department||Department of Electrical Engineering||Supervisors||Professor Yitzhak Birk|
|Professor Shmuel Wimer|
Interconnect shielding is used in VLSI to mitigate the interference caused by the cross-coupling capacitance between adjacent signal lines. The most commonly shielded signal is the clock signal. As the clock signal is disseminated across the silicon die, it experiences unequal propagation delays, which are later balanced out by delay-buffer insertion, and are subjected to a wide, unpredictable change due to process variation.
It has been observed that shielding side effect is a reduction in signal propagation speed. The slowdown depends on the distance between the signal line and the shield lines running parallel to it. In this research, we explore the use of shielding to achieve the required relative delays instead of (or as a partial replacement to) the commonly used delay buffers. Wire-shield delay tuning has several advantages over delay buffers: First, wires are considerably less sensitive to manufacturing process variations than the delay buffers, thereby enhancing the design robustness. Second, design changes, also called Engineering Change Orders (ECOs), are usually required to meet timing specifications while imposing layout changes; The implementation of ECOs using wire shielding results in a much lighter layout footprint, thereby contributing to the project’s schedule. Third, the shield lines are already there, so there is virtually no hardware or power penalty.
In this study, we explored two main issues:
• Scope of applicability: To this end, we determine the delay tuning range that shielding can achieve and the resulting variation values. We found that with shielding alone, a typically used clock segment can be tuned from 12% to 25% out of a nominal delay while attaining half of the buffer delay variability. A stepwise, easy-to-compute wire-shield space-tapering formula, which results in minimum routing resources, is presented as well. We utilize the smaller delay variability to develop a low-variability Clock Tree Synthesis tool (CTS) that can reduce the circuit-design margins. The tool was tested on two industrial 28nm designs of an ARM? CPU and memory controller, resulting in increased operation frequency.
• Delay-measurement framework: Using shields as delay elements requires knowledge of their behavior in real silicon, which may differ from SPICE simulation extracted delay. Because of a lack of observability of internal nodes, directly measuring delays in silicon is very expensive and, in many cases, impossible. To this end, we designed, manufactured, and measured a 16nm CMOS ring oscillator with built-in configurable shielding, accompanied by a proposed delay-estimation methodology. Combining the aforementioned design and methodology, one can derive accurate shielding delays without any direct measurements. By using the proposed combination on a fabricated 16nm chip, we found that a shield delay can tune up to 25% of the segment delay, while on chip variation remains relativity small, around 2%. An estimation for the typically used clock segment demonstrated delay tuning from 10% to 15%, proving the shield delay to be a high-resolution mechanism with a low-variability delay.
Thus, our study is an important step toward the ubiquitous use of shield delays in VLSI circuits.