|M.Sc Student||Talati Nishil|
|Subject||Design of a Memory Controller to Support PIM Operations|
|Department||Department of Electrical and Computer Engineering||Supervisor||ASSOCIATE PROF. Shahar Kvatinsky|
|Full Thesis text|
Given technological constraints of a memory technology, the memory controller in a computing system is responsible for intelligently scheduling memory accesses to optimize system performance and energy efficiency. Existing memory controllers target charge-based DRAM, which has been the technology choice for building main memory for several decades due to its relatively low latency and low cost. DRAM uses charge stored in a capacitor to represent a logical value, and this capacitor is accessed by a transistor. The process technology scaling of DRAM has so far facilitated low cost per area by enabling reduction in cell size, following Moore's law. However, scaling it further to lower technology nodes is becoming increasingly difficult primarily because of difficulty in fabricating capacitors at lower technology nodes. Furthermore, since conventional DRAM memory cells cannot process data, modern computing systems suffer from high latency and energy of data transfer between CPU and memory, commonly known as the von Neumann bottleneck.
In this dissertation, we propose to employ resistance-based emerging memory technology called Resistive RAM (RRAM) to build main memory because of its several advantages such as low cost, better scalability, and higher density. Despite these attractive features, some of the shortcomings of RRAM include high access latency and switching energy, and we propose to address them by designing a customized memory controller for RRAM. While most previous RRAM designs use a traditional DRAM-based memory controller, which cannot unleash full potential for RRAM, we experimentally show using SPEC CPU2006 benchmarks that a memory controller for RRAM designed around technological constraints of RRAM can achieve DRAM-like memory performance and energy efficiency. In addition, RRAM also provides opportunity to perform parallel data processing using the memory cells themselves because of their resistive nature. We further extend our memory controller to support processing-in-memory (PIM) in RRAM using a technique called MAGIC that enables computation without reading data out of the memory array. To this end, we propose R-DDR - an RRAM access protocol similar to DDRx - to perform efficient memory as well as processing operations within RRAM. We show that performing processing inside memory for a data-intensive workload (i.e., query execution for in-memory database), can gain speedup of 5X and can reduce energy consumption by 3.75X compared to state-of-the-art CPU-memory von Neumann model, and hence, alleviate the von Neumann bottleneck.