Ph.D Thesis


Ph.D StudentPort Oron
SubjectDFiant: A Dataflow Hardware Description Language
DepartmentDepartment of Electrical and Computers Engineering
Supervisors PROFESSOR EMERITUS Uri Weiser
ASSOCIATE PROF. Yoav Etsion
Full Thesis textFull thesis text - English Version


Abstract

The most prominent hardware description model has long been the register-transfer level (RTL) design abstraction. The main drawback of the RTL model is its coupling between functionality and timing constraints, resulting in a verbose and less portable code. Two main approaches were taken to mitigate these issues. One approach introduces high-level RTL languages (e.g., Chisel) to improve code expressiveness, but still binds the design to specific timing and device constraints. The other approach relies on high-level synthesis (HLS) tools (e.g., Vivado HLS) that employ software programming languages to abstract over registers. However, these languages lose fine grain hardware control and their inherent sequential semantics inhibit parallel hardware expressiveness.


In this research I propose a new dataflow hardware description abstraction layer which covers the numerous synthesizable uses of RTL constructs and replaces them with higher-level abstractions. I also present DFiant, a Scala-embedded HDL that applies the dataflow semantics to decouple design functionality from its constraints. DFiant provides a strong bit-accurate type-safe foundations to describe hardware in a very concise and portable fashion. The DFiant compiler can automatically pipeline designs to meet performance requirements and produce synthesizable RTL code.

For evaluation, various RTL use-cases were implemented in DFiant, and while lines of code were reduced by more than 70%, performance and utilization stayed roughly the same. Therefore, this work demonstrates high productivity potential in the dataflow hardware abstraction that achieves both correctness and conciseness without sacrificing too much of performance.