|M.Sc Student||Konstantinovsky Iliah|
|Subject||Full Duplex Transceiver based on N-path Filtering|
|Department||Department of Electrical Engineering||Supervisor||Dr. Emmanuel Cohen|
|Full Thesis text|
Current communication systems can be greatly improved by allowing simultaneous transmit and receive operations. One method used for full duplex communication is Frequency Division Duplexing (FDD) communication that allows to communicate in both directions and is based on frequency separation between the receiver and transmitter. The frequency separation allows communication with minimal interference while using common antenna. FDD scheme is commonly used in high throughput communication systems. For example, cellular wireless communication systems 3G & 4G.
The use of a common antenna drives the need for a duplexer to provide the frequency separation. The conventional duplexer is based on high Q elements that are expensive and relatively large. A duplexer based on N-path filtering implemented in CMOS, can reduce the cost and size of such communication systems while maintaining high performance.
This thesis contains three parts in which I analyze, implement and measure this type of duplexer.
The first part contains the design aspects of such an N-Path filter at high frequencies and the analysis done using small signal and Large signal models. One important aspect of the duplexer is its power handling, and it was designed to handle higher output power than 20dBm. As well, the development of a novel model for simulation and analysis of the N-Path filter at high frequencies is presented. This model is verified on Non-Linear simulations of the N-Path filter such as Harmonic Balance and Periodic transient simulations. The models help to analyze high frequency effects and design an N-Path filter with optimal performance.
The second part of the thesis contains the design of a duplexer based on N-Path band pass filter and passive components. The general concept behind this topology is filtering of the noise elevation generated in the Transmitter by a transfer function of the N-Path filter at the Receiver path. The N-Path filter design is targeting for high power handling, low insertion loss and high rejection at close frequencies. Another two-pole topology is inspected which has improved performance, with maximum insertion loss of 2dB and minimum rejection of 20dB 80MHz aside the operation frequency at 5GHz. The aspects of LO Generator design, and negative resistance are shown and studied in order to improve the rejection and insertion loss of such a solution.
In the third section, a test chip fabricated in CMOS technology (TSMC65nm) with the implemented design is described. As well, the process of packaging and design of the evaluation board is shown with simulation supporting optimal system performance. The evaluation board is measured and compared to desired results. The insertion loss of the duplexer is limited by 2dB and the rejection is more than 20dB at an operation frequency of 2.5GHz.
In future work, we will improve the N-Path power handling, LO generation circuit, noise addition and power consumption. As well the study of optimized base band circuitry including negative resistance.