|Ph.D Student||Malits Maria|
|Subject||Thermal and Noise Effects in Nanometer CMOS-SOI Devices and|
|Department||Department of Electrical Engineering||Supervisor||Professor Emeritus Yael Nemirovsky|
|Full Thesis text|
Nowadays, CMOS-SOI is emerging as a promising solution to continue the CMOS scaling allowing low-power, high temperature and “system on chip” applications as well as CMOS-SOI-MEMS/NEMS unique sensing systems for IR and THz imagers. The advantages of SOI technology over standard CMOS are: low power consumption, high operation frequency and high temperature of operation for a given technology node due to the very low source and drain junction capacitances, no body effect and soft-error immunity. While the advantage and importance of CMOS-SOI is well-established, there are two major limiting issues associated with this technology: thermal effects and low-frequency noise.
The role of temperature in Very/Ultra Large Scale Integration (VLSI/ULSI) chips is well-established by now. When the level of power consumption becomes relatively high, a designer has to consider, at the design stage, the effect of temperature on the circuit operation, especially when using CMOS-SOI technology. In CMOS-SOI technology the buried oxide layer introduces a thermal barrier that enhances self and coupled heating effects, degrading the circuit performance. For that reason, it’s important to consider the effect of temperature on the circuit operation at early design stages.
This research addresses the existing gap between the electronic VLSI/ULSI design and the physical aspect of temperature influencing the design. We identify this existing gap as one of the crucial aspects that hinder progress in the field of VLSI. The main goal of this PhD research is to develop an optimal temperature sensor to allow easy on chip thermal management, where the thermal issues are addressed at the initial design phase. This study aims to use the available transistors in the technology under study (CMOS-SOI) as built-in temperature sensors. A unique and novel measurement method based on "Threshold Voltage Thermometry" will be applied to measure chip local temperature. The method will be implemented using a CMOS-SOI Vt extractor circuit to extract transistor threshold voltage on-line.
Another goal of this work is to measure, simulate and develop a model predicting the effect of temperature on low-frequency noise in state-of-the-art advanced CMOS-SOI devices and circuits. Nowadays, it is well recognized that low frequency noise is related to trapping and de-trapping of electrons by tunneling or other thermal processes so it is temperature dependent. Hence, it is important to relate these two major limiting issues, especially in CMOS-SOI technology.