טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentRamadan Misbah
SubjectAdaptive Programming for Multi-Level Cell ReRAM
DepartmentDepartment of Electrical Engineering
Supervisors Professor Ran Ginosar
Professor Shahar Kvatinsky
Full Thesis textFull thesis text - English Version


Abstract

The memristor is a two-terminal device that can be programmed to two boundary resistances, Low Resistance State (LRS) and High Resistance State (HRS). Zero static power, low density, CMOS compatibility, and non-volatility are among the characteristics that make memristors a strong candidate for non-volatile memory design. At the same time, these unique characteristics also make memristors difficult to model. The TEAM and VTEAM models are two generic and reliable models that are able to overcome these challenges and are thus considered suitable for modeling a wide range of memristive applications.

Memristors are used as memory cells in resistive-based memory modules (i.e., ReRAM, Resistive Random Access Memory) and are considered attractive candidates to replace FLASH memories, with their limited scaling, in modern processes. The memristive state of the ReRAM cell is set to either LRS and HRS to store, respectively, logical '1' and logical '0'. To increase ReRAM density, it is possible to program the memristor to intermediate resistance between LRS and HRS, hence achieving multi-level storage capability (MLC). However, the nonlinearity of memristors leads to non-uniform distribution of resistance levels when using identical Constant Voltage Stress (CVS) pulses to program a cell. Furthermore, because cells in ReRAM deviate from each other as a result of process variations, the levels in MLC ReRAM must be represented by a sufficient resistance range rather than a deterministic resistance value. Otherwise, non-uniformity will lead to an overlap between resistance levels, increasing the probability of erroneous read operations.

MLC memristive memories use various programming schemes to overcome the problem of non-uniform level distribution. Program and Verify (P&V) techniques, Incremental Magnitude Pulse Programming (IMPP), and Incremental Length Pulse Programming (ILPP) are the common solutions. The IMPP and ILPP techniques compensate for the slowdown in the resistance transition caused by the nonlinearity of memristors by applying consecutive pulses of increasing magnitude and length, respectively. In contrast, P&V programming techniques apply programming pulses followed by verify pulses to confirm that the cells are programmed to the desired level.

In this thesis, we study the effect of nonlinearity on the device tolerance to process variation. We present Adaptive Programming (AP) - a programming method that improves process variation tolerance by effectively linearizing the memory cell, and show that AP reduces the erroneous cell count in terms of FoE by almost 50%. We also show that AP is compatible with crossbar architecture while using selectors to mitigate sneak-path currents in MLC ReRAM. Moreover, we show that the AP method requires fewer programming steps than previously proposed MLC programming techniques such as P&V, which results in faster programming and energy reduction of up to 95% compared to P&V. Finally, we show that AP enables in-memory multi-valued computing that can be used in non-von Neumann machines.