|Ph.D Student||Beer Gingold Salomon Michel|
|Subject||Metastability and Synchronization in VLSI systems|
|Department||Department of Electrical Engineering||Supervisor||Professor Ran Ginosar|
|Full Thesis text|
System on Chip (SoC) designs typically employ multiple clock domains due to the need to interface several external clocked circuits operating at different frequencies, the use of IP-cores that operate at varying clock frequencies for power-speed trade-offs, and the power and area advantage of breaking large clock trees into multiple small ones. The principal challenge of such Globally Asynchronous Locally Synchronous (GALS) architecture is the need to communicate through the different clock domains. In this context, reliable low-cost low-latency high-throughput communication and synchronization is of great interest. Such synchronizations are often susceptible to metastability effects, which may propagate into the receiving circuit and cause malfunctioning.
While synchronization circuits and metastability models have been widely investigated, often the conclusions obtained are based on empirical results and the metastability mechanism and synchronization circuits' tradeoffs are not completely understood. Moreover, ultra-deep sub-micron technologies provide new challenges in synchronization that should be accounted for when designing reliable systems.
This research deals with metastability and synchronization challenges in three levels. The first level investigates metastability models providing novel formulas and extending existing results. In this context, the basic mean-time-between-failures (MTBF) formula is extended for coherent clock scenarios showing non-uniform characteristics. Mathematical formulations of simple synchronization elements are studied and a new model for multi-stage synchronizers is developed. A new model to predict supply voltage and temperature variations on MTBF is also formulated and analyzed. The second level investigates synchronization circuits. While today library flip-flops are optimized mostly for delay, there is no consideration from the synchronization point of view. The effect of cell size, circuit topology and other architectural variables is considered. The effect of feedback in flip-flops and latches used in synchronizers in order to accelerate output from metastability is investigated. We also propose an adaptive synchronization scheme in order to adapt to on-chip variations in deep-submicron technologies. The third level corresponds to the development of novel simulation and measurement methods for metastability. An extended simulation method was proposed which corrected a common error present in other publications. The research develops metastability measurement methods and compares delay based measurement methods and variable-frequency measuring methods. Using these principles, on-chip circuits are fabricated and measurements are compared to classical direct measurements of synchronization parameters. We build these circuits in FPGAs (130nm, 90nm and 65nm) and a test chip in 65nm technology in order to obtain empirical measurements of our findings. Often measurements also lead us to some novel research findings