|Ph.D Student||Kedar Gil|
|Subject||Hardware/Software Co-Design to Minimize Energy in|
|Department||Department of Electrical Engineering||Supervisors||Professor Avi Mendelson|
|Professor Emeritus Israel Cidon|
|Full Thesis text|
Hard real-time systems are common in various systems, such as automobiles, airplanes, industry machine and communication systems. Hard real-time systems are unique since the tasks are executed with defined deadlines as opposed to general purpose systems where the common aim is to the increase the throughput. Real-time systems are commonly implemented on embedded system architecture with special operating systems supporting real-time scheduling. The developing process is comprised of a hardware specific compiler, a worst-case execution time (WCET) estimation tool and a real-time scheduler which considers the task WCETs.
Energy is a major concern in embedded system since it affects the battery consumption and for cars also affects the air pollution. Current architectures support power management mechanisms mainly at two levels; using voltage and frequency scaling (DVFS) in order to save dynamic core power and dynamic power management (DPM), which aims to decreases the core static power.
In this thesis, we investigated how energy can be saved at all levels of the system starting at analyzing and optimizing at the application level, enhancing the scheduling mechanisms and up to new hardware primitives.
At the Hardware level, we developed new cache architecture named SPACE (Semi-Partitioned CachE), which enables sharing of data and instruction between parallel application tasks in multi-core system. Our cache enables sharing data between multiple producers and consumers. We showed that using our novel cache architecture decreases the system energy consumption in an average of 34%.
For the scheduling level, we developed two new scheduling algorithms for minimum energy. Energy oriented EDF (EO-EDF) scheduling algorithm, which changes the execution order of the tasks according to the tasks attributes to decrease the core's energy consumption for single core systems. We showed that the EO-EDF algorithm decreases the core's energy consumption by an average of 30%. The second scheduling algorithm, considers the task cache footprints and DVFS sensitivity to define the task allocation and execution order for multi-core architectures. We showed that our heuristic algorithm results in near optimal scheduling.
For the compiler level, we developed an optimization algorithm which analyzes the binary code to find appropriate places to add a data pre-fetch instruction. By adding the pre-fetch instruction the required data is fetched to the L1 cache without increasing the instruction cache miss count, which results in lower task's WCET. We showed that our optimization decreases the task's WCET by an average of 11%.