M.Sc Thesis

M.Sc StudentMeshi Yinnon
SubjectFlex: Optimal Energy Efficiency in Asymmetric
Computer Architecture
DepartmentDepartment of Electrical and Computer Engineering
Supervisors PROFESSOR EMERITUS Uri Weiser
PROF. Isaac Keslassy
Full Thesis textFull thesis text - English Version


In recent years, the demand for lower energy consumption of computer systems increased, along with the need for higher performance. Minimizing energy consumption of modern CPUs is needed both for small portable devices that require longer battery life, as well as to reduce electricity costs of high-end computer systems.

However, as process generations advance, it becomes harder to provide higher performance and lower energy. In the past, each new process generation provided faster transistors that were also more power efficient, compared to the previous generation. Nowadays, since the transistors operating voltage cannot be further reduced, the improvement in the transistors power efficiency diminishes. The diminishment in power efficiency leads to what is called "dark silicon", which means that it will not be possible to operate all the chip's transistors at full speed due to power and thermal constraints. Another limitation is the increasing difficulty of improving single core performance as a square root of its size.

One of the approaches to improved performance and power efficiency is by Asymmetric Multicore Processor (AMP) architecture, commonly composed of a big serial core, and many small parallel cores. This asymmetric architecture enables acceleration of both the serial and parallel portions of the program. It was shown that, in many cases, the AMP architecture can provide higher maximal performance and better power efficiency, when compared to a symmetric architecture composed of several cores of the same size.

This dissertation studies the energy efficiency of AMP structures, focusing on the entire performance range that the system can provide, since many applications (such as video processing or communication) require a specific computation time, and do not benefit from higher performance. We show that while AMP architectures are energy-efficient for either low or high performance demands, they are inefficient for mid-range performance requirements. We then propose FleX, an architecture composed of several big cores with varying sizes, and many one-sized small cores. FleX represents the lower envelope for energy consumption of a given AMP structure. Given the characteristics of the program and the required performance, we determine the optimal configuration to minimize energy consumption, that is the number of small cores and the size of the big core that should be used, as well as their operating frequencies for serial and parallel workload parts.

Furthermore, we present 2D-FleX, a practical solution for next-generation chip architectures, consisting of only two big core types (large, medium). 2D-FleX aims to narrow the energy gap between AMP and the optimal solution represented by FleX. We then propose a simple heuristic, with which we determine the optimal size of the additional medium core.

When comparing an example 2D-FleX structure consisting of a medium core that is chosen by using our proposed heuristic, maximal energy waste is reduced from 20%-35% to 6%-12% compared to an AMP structure consisting of a single big core.