|M.Sc Student||Zhang Yongxin|
|Subject||High Speed Receiver Circuit for On-Chip Communications|
|Department||Department of Electrical and Computer Engineering||Supervisors||PROFESSOR EMERITUS Ran Ginosar|
|DR. Aharon Unikovski (Deceased)|
As System-On-Chip (SOC) integrates a growing number of modules, and since global On-Chip Interconnect does not scale with technology, it’s a big challenge to achieve the long range high-speed on-chip data communication. The typical bit-parallel on-chip communication solutions may suit for the high data rate demand but they induce a high cost of area, noise and power and also growing routing difficulties.
A high-speed bit-serial link that incorporates fast clock generator, two-phase non return to zero (NRZ) Level Encoded Dual Rail (LEDR) asynchronous protocol, serializer and de-serializer using fast asynchronous shift registers, LEDR decoder and differential channel encoding is described. This link that can enable one gate (FO4) delay speed, around 10Gbps under the Tower 180nm Technology, is employed in this research.
The research deals with the design of the high-speed asynchronous analog transmitter and receiver circuit over 10mm transmission line that can satisfy the high speed requirement. A current mode (CM) analog transmitter and receiver pair is explored. Compared with the voltage mode (VM) circuit, it can give lower swing, lower dynamic power and enable longer distance and faster operation. A typical kind of analog CM TX circuit is adopted and an improved version is proposed for our asynchronous application.
From the optical communication community, we adopted an enhanced common gate trans-impedance receiver configuration - the regulated-cascoded trans-impedance amplifier (RGC TIA) which is very effectively in relaxing the big input capacitance from bandwidth determination. Due to the different applications from the optical communication, we make some modifications to the circuit.
We also propose a very simple VM circuit for analog transceiver. Just use 2 stages of inverter as the analog TX and 2 stages of the inverter as the analog RX. It shows better results both for the power and speed consideration compared with the RGC TIA.
To get the link performance from simulation, a RLC model for transmission line is used. We use HFSS electro-magnetic solver to get the parameters of the RLC model at a certain frequency. For higher accuracy, I exported the layout of the transmission line from Cadence to HFSS to get the S-parameter of it which can be exported back to Cadence for simulation.
A test chip (FOX2) that consists of 30 links with different transmission line lengths and operational modes is designed and fabricated. Because of limited available metal layers, only M6 layer is used as transmission line. Test environment that consists of PCB board holds FOX2 chips and a LabView GUI controls the board is designed.
Test result shows the chip works. The FO4 delay of the chip is around 8.7Gbps based on the result from the RingOS test circuit. However many links cannot get the correct data after the data transmission so it’s hard to declare the link performance. One voltage mode link with 1.74mm transmission line can work without bit error until the frequency of 4.1Gbps under 1.8V supply voltage which means the analog transceiver and the digital blocks in the link can work at that speed.