M.Sc Thesis
M.Sc Student Awad Morad An Analytical Model for the Silicon Limit of Single and Double RESURF Drift Layers in Integrated LDMOS Devices Department of Electrical Engineering Professor Dan Ritter Dr. Shye Shapira

Abstract

Power Management Integrated Circuits (PMIC) are a monolithic form of voltage and current regulation circuits that allow miniaturization of power supplies in all mobile and other electronic systems. At the heart of these systems are integrated high voltage power switches, mostly based on Lateral Diffused Metal Oxide Semiconductor (LDMOS) Transistors. The LDMOS high voltage capabilities are enabled by a low doped diffusion layer called the drift layer. Drift layers with a high breakdown voltage capability also have a high specific resistance (sRon) which causes conductive losses. The most important optimization goal in the design of high voltage power devices is minimizing the conductive loss by reducing sRon. An important theoretical aid for such design is the calculation of the lowest limit of sRon theoretically attainable for a given breakdown voltage. This relation is called, the “Silicon Limit” and has a simple physics based, theoretical model for a vertical one dimensional drift layer.

Two dimensional reduced surface electric field (RESURF) diodes have been extensively used for the design of as LDMOS transistors and other high voltage devices. However for such structures a solid analytical model is lacking. Thus, most of the optimization of LDMOS transistors is performed by computational and physical trial and error methods. Therefore, analytic modeling of the relation between the resistance, design parameters and breakdown voltage is crucial to meet and exceed the design requirements for power efficiency and production costs.

We have developed an analytical model that fully describes RESURF diodes. The model is based on a solution of the two dimensional Poisson equation under specified assumptions and boundary limits. We provide for the first time an analytic expression for the two-dimensional silicon limit (minimal resistance of RESURF diode) as a function of breakdown voltage and the various design parameters (dimensions and doping levels) that achieve the silicon limit. Moreover, the model calculates all possible solutions for a given breakdown voltage (beside the optimal one) enabling a full description of RESURF diodes. The model also allows choosing the best solution under production constraints such as a limit to the thickness of the drift layer. The model that was developed to describe single RESURF devices, is then extended to double RESURF diodes. It is systematically validated against Technology Computer Assisted Design (TCAD) simulations of the diode and published experimental data. The two dimensional Silicon limit calculated here for the first time turns out to be approximately half of the value of the one dimensional Silicon limit. The significance of this result is that optimized lateral, RESURF based, two dimensional devices can have lower sRon than optimized vertical discrete DMOS devices.