|Ph.D Student||Krylov Igor|
|Subject||Nano-Scale Atomic Layer Deposited Dielectrics for InGaAs|
|Department||Department of Nanoscience and Nanotechnology||Supervisors||Professor Dan Ritter|
|Professor Emeritus Moshe Eizenberg|
|Full Thesis text|
Introduction of new channel materials into the silicon metal oxide semiconductor field effect transistor (MOSFET) technology is one of the options to continue device scaling beyond the silicon limit. The III-V compound semiconductors are leading candidates for n-channel MOSFET material due to their superior (compared to Si) electron transport properties. Among these materials, InGaAs is the optimal choice due to the combination of high injection velocity and appropriate bandgap. The main drawback of this semiconductor is the lack of stable native oxides. Therefore, gate dielectrics must be deposited directly on InGaAs during device fabrication, usually by atomic layer deposition (ALD). The ALD technique is also currently used in advanced silicon MOSFET technology for high quality gate dielectrics having higher dielectric constants than SiO2.
In this work, a detailed study of InGaAs based MOS gate stacks with different ALD gate dielectrics material, was carried out. Electrical as well as analytic techniques, were employed to better understand the dielectric/InGaAs interface.
Metal-oxide-semiconductor (MOS) capacitors, that are the main component of any MOSFET device, were tested for the electrical characterization of the gate dielectrics. Pure Al2O3, HfO2 and AlN dielectrics, as well the advanced Hf-O-Al based dielectric structures, were investigated. The quality of the semiconductor-insulator was studied, and the role of pre-deposition treatments and post deposition annealing was examined. The findings, allow formulating a passivation concept for InGaAs based MOS devices. The role of different interface trap types on the commonly observed C-V non-ideal phenomena, namely dispersion in accumulation, C-V "hump" and hysteresis, is also discussed.