|M.Sc Student||Stanislavsky Amnon|
|Subject||Power Driven Floorplan and Energy Efficient Adders|
|Department||Department of Electrical and Computer Engineering||Supervisors||PROFESSOR EMERITUS Avinoam Kolodny|
|ASSOCIATE PROF. Shmuel Wimer|
In the first part of this Thesis - a method for performing power driven floorplan is presented. The concepts of power paths and connectivity matrix are presented and explained. An algorithm for transforming a power path based graph to a connectivity matrix is presented. Since simulated annealing is used to achieve optimal floorplan - the weight function of a floorplan is thoroughly explored and explained. A tool which performs power driven floorplan was built and tested. Several academic examples are presented and discussed. Finally an example from the industry is presented. Unfortunately power driven floorplan which doesn’t rely on congestion avoidance leads to little to no improvement in power consumption .
In the second part of this Thesis - Energy efficient adder design based on two-sided carry computation is proposed. Addition takes place by considering the carry as propagating forwards from the LSB and as propagating backwards from the MSB. The incidence at a midpoint significantly accelerates the addition. This acceleration together with mixing low-cost ripple-carry and carry-chain circuits, yields energy efficiency compared to other adder architectures. The optimal midpoint is analytically formulated and its closed-form expression is derived. To avoid the quadratic RC delay growth in a long carry chain, optimal repeater insertion is used. The adder is enhanced in a tree-like structure for further acceleration. 64 and 128 bit adders targeting 500MHz and 1GHz clock frequencies were designed in 65 nanometer technology. They consumed 15% to 20% less energy and area compared to adders generated by a state-of-the-art EDA synthesis tool.