טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
Ph.D Thesis
Ph.D StudentBerman Amit
SubjectNon-Volatile Memory Enhancement: A Cross-Layer
Approach
DepartmentDepartment of Electrical Engineering
Supervisor Professor Yitzhak Birk
Full Thesis textFull thesis text - English Version


Abstract

The invention of semiconductor technology has marked a new era in memory devices: SRAM, DRAM, Flash and more. The ever-increasing rate of data production and consumption stimulates the development of high-performance memory devices. At times, high-density scaling drives new applications and ways of operation. However, device advancement presents trade-offs and ever growing challenges.

High-performance memory (SRAM, DRAM) suffers from relatively low density, higher power consumption and, most important, data volatility. Similarly, high-density, non-volatile memory (Flash) exhibits relatively low performance. As device technology shrinks, massive inter-cell interference is limiting the achievable density, high variations among memory cells result in degraded read/write performance, and endurance is limited due to cell degradation. Over the past decade, the various challenges have been the subject of much research, mostly focused on technology- and circuit-level innovation. Other challenges (e.g. restricted overwrite due to one-way charge level changes) were addressed by coding techniques.

In our research, we explore cross-layer methods for enhancing memory characteristics (density, read/write performance, power and reliability). Specifically, inter-cell interference is mitigated by using constrained coding to prevent the data patterns that cause interference beyond a predefined limit; read performance is improved by way of a speculative early sensing mechanism, whereby cell read time is dynamically minimized through premature sensing along with guaranteed error detection; multi-level cell write speed is improved by minimal maximum-level programming, whereby cells are being written gradually, different same-size pages are stored in different numbers of cells, and bit fractions of any given page are stored in a cell; and the number of possible rewrites between block erasures is increased via page management that permits writing to retired pages when proper data is available. Our schemes are presented and evaluated mostly in the context of NAND Flash, with several extensions to DRAM and SRAM, but some are also applicable to emerging memory technologies such as PCM.


*parts of this thesis may be covered by patents