M.Sc Thesis

M.Sc StudentPolishuk Leon
SubjectLatency considerations for NoC interconnection fabrics
DepartmentDepartment of Electrical and Computer Engineering
Supervisors PROFESSOR EMERITUS Avinoam Kolodny


Network on Chip (NoC) emerged in the last decade as a solution for connecting multiple modules on a single silicon die. This technique is inspired by computer networks and consists of multiple routers connected by links. NoC has many advantages: high throughput, scalability and low resources. However, due to its latency, the adoption of NoC in the industry is relatively slow.

In our work, we present a mathematical model to analyze NoC latency. We model the latency caused by wires and examine techniques to reduce it.  Router latency model for various NoC architectures is presented as well. Using these models, we compare different NoC architectures latency-wise. The comparison is made for various operating points. Each operating point contains information such as NoC size, communication pattern (local or global), system operating frequency, etc.

For our research, we choose four architectures: Simple Mesh, PyraMesh, EVC and HNoC. The Simple Mesh is the most common architecture in the literature and all other architectures based on it. Each one of the remaining architectures represents a different approach for on-chip communication. The PyraMesh is a hierarchical architecture, which adds routers and interconnect layers in order to reduce the number of routers a messages passes on its way. The EVC represents smarter routers, which make the messages to bypass most of the routing stages on their way. The HNoC adds buses between adjacent modules, in order to cancel the network’s overhead for messages traveling between nearest neighbors.

We divide the comparison into two main categories according to system’s clock. The first is slow systems, in which the operating frequency is relatively low. The advantage of these systems is their low power dissipation. The second category is fast systems, in which the network operates at its maximal possible frequency. The advantage of these systems is the high speed of computation.

System parameters such as NoC size, technology node and operating frequency are known early in the design process. Communication patterns can be estimated according to the designated applications at the same design stage. Choosing the most suitable architecture reduces the mean latency by an average of 1.4X and up to 2X with respect to the base case. Using the tools we present in our research, the designers are able to select the best architecture based on their needs during system planning, reducing the latency and saving valuable development time.