|Ph.D Student||Ben-Itzhak Yaniv|
|Subject||Advanced Heterogeneous NoC Design|
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Avinoam Kolodny|
|Professor Emeritus Israel Cidon|
|Full Thesis text|
Networks-on-Chip (NoC) is a communication subsystem on a chip, typically between IP cores in a system on a chip (SoC) or in a chip multi-processor (CMP). NoC technology applies networking theory and methods to on-chip communication and brings notable improvements over conventional bus and crossbar interconnections. NoC improves scalability, bandwidth, latency and power efficiency.
SoC and CMP designs use Networks-on-Chip (NoC) to support a variety of inter-module communication bandwidth and latency requirements. In both cases, NoC performance requirements are usually heterogeneous in terms of particular module-to-module bandwidth and delay, as traffic is usually distributed unevenly across the chip. Therefore, it is expected that the optimal NoC designed to support these requirements should also be heterogeneous in terms of link capacities and number of virtual channels (VCs) for each unidirectional port.
In the first part, we present a heterogeneous NoC simulator (called HNOCS). HNOCS is an event driven simulation, based on OMNeT simulation framework. It supports heterogeneous NoC configuration in terms of capacity and number of VCs for each link. Most of existing NoC simulators are either proprietary or built on non-standard infrastructure. Therefore, we published HNOCS as an open-source NoC simulator.
In the second part, we introduce a novel evaluation methodology to analyze the delay of a wormhole routing based heterogeneous NoC. This methodology can be utilized to analyze different heterogeneous NoC architectures and traffic scenarios for which no analysis framework has been developed before. It introduces a set of implicit equations, which can be efficiently solved iteratively.
In the third part, we develop a novel design methodology that optimizes capacity of each link in a NoC and the numbers of virtual channels at each router port for a specified set of flows and latency constraints. In order to lower computation costs of the design methodology, we utilize the aforementioned analysis thus replacing the need for NoC simulation. Furthermore, we demonstrate that there is a possible trade-off between the total capacity of links and the total number of VCs; hence, offering more than one optimal heterogeneous NoC design.
In the fourth part, we introduce a heterogeneous NoC router architecture. The NoC router is based on shared-buffer router architecture and has the advantages of ingress and egress bandwidth decoupling, and better performance as compared with input-buffer router architecture. We also introduce and formally prove a novel approach that reduces the number of required middle shared-buffers without affecting the router performance.