|M.Sc Student||Jacob Prarthana|
|Subject||Testing of a Fast on Chip Serial Link|
|Department||Department of Electrical and Computer Engineering||Supervisor||PROFESSOR EMERITUS Ran Ginosar|
|Full Thesis text|
Increased complexity and aggressive scaling of technology has adverse effects on interconnect performance. To determine circuit performance and reliability, interconnect has become the ruling factor. The thought of using parallel links may increase the data transmission speed in hand giving rise to high contention or even low resource utilization. Novel serial link is proposed to overcome all these effects and its efficiency and optimization results.
In this work low power fast differential serial link for on chip long range interconnects is investigated. The data flows through the serial link in following steps firstly through Synchronizer followed by serializing and encoding into channel wires and at receiver all the procedure is reversed. The uncoded parallel data is first serialized and then fed into wires which at receiver are again converted into parallel stream The unique circuits used in serializing and deserializing encoding and channel wires gives us the fastest data transmission rate. To the best of our knowledge this is proved to be fastest till now having 28Gbps at 65nm through simulations.
I present test and verification of the proposed high data rate serial link. To prove our concept along with its components on real 65nm 10 LP process we had our built in self-test. I present my part of testing fast serial link. The primary part was to find out the FO4 delay of our technology 65nm for which a ring oscillator circuit was built and simulated. A clock generator circuit was built to generate clock signal for data synchronizing inside SRs in which it was crucial to find out its frequency range by calculating delay of single delay element. To accomplish this target a delay structure was simulated. A Transmitter current test circuit was built to follows the changes at the input of channels receiver which would keep the output in required range. Finally the output from the channels receiver need to be shifted and biased to half Vdd this requirement was fulfilled by output stage circuit.
Final part concentrates on building test environment for testing the chip which includes designing the analog board, digital board and a PC (having an NI lab view based GUI). After which the operating procedure of test environment is detailed. Regarding testing and getting results was unsuccessful because of error in digital controller inside chip.