|M.Sc Student||Weindling Sammy|
|Subject||Platinum Embedded Nanodots for Non Volatile Memory|
Fully Implemented by Atomic Layer Deposition
|Department||Department of Electrical and Computer Engineering||Supervisor||PROFESSOR EMERITUS Yosef Salzman|
|Full Thesis text|
Floating-gate non volatile memory (NVM) structures with embedded nanodots surrounded by high-k dielectrics are attractive candidates for high-density storage devices in advanced technology nodes. The high work-function difference between a silicon substrate and metal nanodot enables efficient storage of charge carriers, improving retention properties. A high-k dielectric layer is used to scale down capacitors without compromising retention properties.
The first part of this work deals with theoretical model for discharging process. Non correlation between theoretical results based on coherent tunnelling through the tunnelling layer, and experimental results leads us to consider a non coherent trap-assisted tunnelling phenomenon for retention properties. Contaminations, which are introduced during exposition of the wafer to ambient atmosphere, play the role of traps at the interface between tunnelling layer and Pt nanodots.
To decrease contaminations in the structure, Atomic Layer Deposition (ALD) techniques are used. ALD is a self-limiting periodic surface adsorption deposition technique, which leads to conformal films. Optimization on the HfO2 growth process emphasizes the presence of a hardly-controllable amorphous interfacial layer between the substrate and the dielectric. To face this issue, thermal SiO2 are used as tunnelling layer, because of its high quality interface with Si.
In this work NVM capacitors based on SiO2 and HfO2 tunnelling and blocking layers with embedded Pt nanodots have been developed with ALD (ALD-sample) and electron beam gun evaporator (EBG-sample) techniques. Both memory window and retention properties are found to be worse for ALD-sample than for EBG-sample. Based on the experimentally observed temperature-dependence in charge retention times, the discharging mechanism of these devices - especially ALD-sample - are attributed to trap-related emission processes. Traps presence is mainly due to contaminations introduced during the fabrication process and multiple exposition of the sample to ambient atmosphere during the process.
To cope with this issue, an all ALD with in situ Pt dot deposition is performed. The wafer is introduced in the ALD chamber to perform Pt nanodots growth. HfO2 blocking layer is deposited without extracting the wafer from the ALD reactor. This new sample shows better retention properties than the previous samples (a third of the initial total charge is stored after ten years).
This work may lead to the introduction of new NVM fabrication concepts useful to increase retention properties and thus to scale down devices.