|M.Sc Student||Even Zur Ziv|
|Subject||Non-Volatile Memories Based on Silicon Nanowires|
|Department||Department of Electrical Engineering||Supervisors||Dr. Yuval Yaish|
|Professor Nir Tessler|
|Full Thesis text|
Nanoparticles memory is a promising memory type which harnesses metal nanoparticles and quantum mechanical tunneling current for charge storage. This thesis presents the work done to fabricate and test the memory effects in nanoparticles embedded metal-oxide-semiconductor planar capacitors, bottom-up and top-down Silicon Nanowires transistors. All fabricated devices are based on Au nanoparticles (NPs) as charge trapping centers. Gate dielectrics included high-k layers and thermally grown oxide. Source and drain electrodes of the transistors were fabricated using Nickel-Silicide process. Both Au NPs and Nickel-Silicide formation process steps involve Post Deposition Annealing with reference to the tunneling layer dielectric. The high frequency capacitance characteristics reveal counter clockwise hysteresis which is evidence for the memory effect controlled by Si - NPs tunneling crosstalk. A hysteresis of 7 V is demonstrated which is large enough to enable the use of nanoparticles embedded devices as memory devices. The transistors were studied by current vs. gate voltage and current vs. source-drain bias measurements. The results show that the NPs have a negligible effect on the counter-clockwise hysteresis and charge retention for the different transistors that have been studied. We believe that interface charged traps overwhelmed the contribution from the intentional deposited NPs.