|M.Sc Student||Vishnyakov Victorya|
|Subject||Inductive Effects in On-Chip Interconnects|
|Department||Department of Electrical and Computer Engineering||Supervisors||PROFESSOR EMERITUS Avinoam Kolodny|
|PROF. Aby Friedman|
Global on-chip interconnect do not scale with reduced feature size due to increased design complexity, demand for integration and technology constrains. As a result, as technology progresses, the effect of interconnect on the performance of high speed and high density integrated circuit increases. With shorter rise times and lack of scaling in the length of global wires, the inductive effects exhibited in wires of upper metal layers cannot be neglected.
Crosstalk noise in on-chip interconnect plays a major role in the performance of modern integrated circuits by causing logic failures, affecting the delays and increasing the delay uncertainty. In the presence of inductance, capacitive and inductive coupling noise as well as multi-aggressors will occur, complicating both the modeling and mitigation of the noise. Long range inductive coupling is added to the already strong capacitive coupling in global interconnect lines, and noise analysis and mitigation cannot be limited to nearest neighbors. Simultaneous capacitive and inductive coupling, together with multi aggressors scenarios becomes the main risk to the signal integrity of the global interconnects.
In this work, coupling noise in on-chip interconnects and its effect on design optimizations of global interconnects is investigated. The differences between capacitive and inductive coupling are discussed and design guidelines for noise analysis and mitigation are formulated. A novel method to model and analyze noise in multi-line structures is proposed, exhibiting an error of up to 9% as compared to SPICE. This method is physically intuitive since it decomposes the noise produced by each of the aggressors into individual capacitive and inductive noise sources. The proposed model and related layout oriented noise mitigation guidelines are applied to crosstalk noise reduction in multi-line structures.
In addition, analysis of inductive effects trends over time is performed based on technology scaling predictions. The existence and magnitude of frequency dependent effects are evaluated. It is shown that the frequency dependent effects in global interconnect decrease as technology progresses since the scaling in line dimensions is more significant than the frequency increase. To understand the importance of inductive effects over time, inductance figures of merit are evaluated under the process predictions assumptions. It is shown that as technology progresses, the inductive effects become less critical from one process generation to another. In addition, it is shown that the inductance figures of merit should be adjusted to include the constraints on repeater insertion and updated expressions for the figures of merit are proposed.