|M.Sc Student||Sizikov Gregory|
|Subject||Design and Analysis of integrated voltage regulators|
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Avinoam Kolodny|
|Mr. Michael Zelikson|
|Professor Aby Friedman|
|Full Thesis text|
This research is dedicated to efficiency analysis of on chip DC-DC converters using an air-core inductor in the package. Two key integration challenges are discussed. First is the scaling of the output LC filter. It is shown that the LC filter scaling results in high switching frequency of the converter. Second is the usage of modern, sub micron, process for power circuitry. Efficiency is becoming very critical when the DC-DC converter is integrated in the same IC with the load because the converter and the load share the same thermal/performance budget. Therefore efficiency optimization is the major goal of this research. A simple yet intuitive losses model is presented. It includes major power components of the DC-DC converters, i.e., power FETS, the inductor and in certain case the output capacitor. An analytic expression is derived for the losses. The key innovation of the analytic model is that skin effect in the package embedded inductor is captured by a frequency dependent formula and a ladder model in SPICE. Several efficiency optimizations are performed based on the analytic model. It is shows that the peak efficiency is achieved when switching frequency dependent losses are exactly equal to switching frequency independent losses. It is shown that the switching frequency can be optimized independently of the load current. It is shown that considering the frequency dependent model of the inductor results in a switching frequency that reduces the converter losses by 15%. Later on the proposed switching frequency optimization with power FET area scaling is applied as light load efficiency mechanism. The result is that increasing switching frequency improves efficiency at light load. The intuitive explanation of this result is that in high current ripple mode due to low inductance of the output filter the rise in switching frequency reduces the current ripple and the improvement is quadratic where as CVF losses degrade linearly only. It is shown that the light load efficiency can improve by up to 25% using the proposed optimization method. Full SPICE closed loop simulation deck was built to verify the analytic results. Very good match was observed between spice and analytic results.