M.Sc Thesis

M.Sc StudentKouslik Elkin Anna
SubjectMacro Models for Power Estimation at RT Level in VLSI
DepartmentDepartment of Electrical and Computer Engineering
Supervisor PROFESSOR EMERITUS Avinoam Kolodny
Full Thesis textFull thesis text - English Version


Early power estimation has become an essential instrument in microprocessor design. It provides feedback on functional block power consumption to design engineers and architects, and allows making tradeoffs between timing, power and area. It enables power reduction and optimization work by providing a measure of power consumption to optimization tools. Power estimation is required at each abstraction level of the design. A well established technique for schematic-level power estimation is extensively used. At RT (Register Transfer) and micro-architectural levels such tools are still a matter of research. We focus our study on RTL power modeling.  The motivation is the necessity to provide quick feedback to RTL designers on proposed incremental changes aimed for power reduction. This feedback should be fast and accurate - it needs to predict block’s power consumption as close as possible to the real circuit power. Using this power model, changes in the design can be evaluated at RTL. Another usage for such macro model is estimating power for long applications for better test coverage and faster project turn-around-time. Since block’s power consumption depends on its circuit implementation details, we use the information available at the gate-level - a precise power estimation tool - to ensure that our model correlates well to the real circuit. This way we exploit the bottom-up modeling approach by learning about power consumption at low level details and abstracting them out to higher level. We propose two generic models. The first one assumes the “black box” approach, where schematic-level nodes’ behavior under different applications is unknown, and the only available information is its power consumption for a given application. The other model assumes “white box” approach - where all gate level implementation details and block’s circuit behavior are available for each test. These approaches cover a major part of possible work scenarios. Both models rely on the concept of assigning each RTL node its effective capacitance, i.e. its equivalent schematic capacitance which is switched when this node toggles. This assignment is based on diving all RTL nodes into disjoint groups, where each group is responsible for some sub-circuit toggling. The methods differ by algorithms for effective capacitances’ assignment. In “black-box” method we use linear programming techniques to derive effective capacitances. In “white-box” technique we propose an algorithm for finding RTL-to-schematic groups correlation which is based on a mapping driven by circuit behavior and its power consumption. A metric for models’ quality estimation is proposed and discussed.