|Ph.D Student||Moiseev Konstantin|
|Subject||Optimization of Interconnects in CMOS Nanoscale Technologies|
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Avinoam Kolodny|
|Professor Shmuel Wimer|
|Full Thesis text|
Design of VLSI circuits has become relatively difficult in the last decade because of continuous technology scaling and as a result, increasing circuit density and complexity. High power consumption, noise effects and strict delay requirements are among the problems that need to be addressed by integrated circuit designers. These problems become more and more severe with new technology generations.
In the last decade a lot of research dedicated to VLSI circuit power reduction has been done. It included development of architectural, logic, circuit and layout facilities for power reduction. At the same time, it is known that interconnect is one of the major causes for dynamic power consumption. Thus, interconnect optimization techniques are of great importance.
This research focuses on development of interconnect optimizations for reduction of VLSI circuit power and / or delay. We propose different layout optimization techniques, which can be applied at the routing stage or in post-routing layout refinement. Special emphasis is placed upon power optimization with timing constraints and investigation of power-delay trade-offs, since interconnect timing may be critical in VLSI design for performance. In some cases it would be preferable to reduce interconnect power by increasing the circuit clock period. We believe that our study will contribute to the theoretical and practical understanding of VLSI layout optimization for power and delay.