|Ph.D Student||Dobkin Rostislav|
|Subject||High-Speed Asynchronous Communication for SoC|
|Department||Department of Electrical Engineering||Supervisors||Professor Ran Ginosar|
|Professor Emeritus Avinoam Kolodny|
|Full Thesis text|
System on Chip (SoC) designs typically employ multiple clock domains due to the need to interface several external clocked circuits operating at different frequencies, the use of IP-cores that operate at varying clock frequencies for power-speed trade-offs, and the power and area advantage of breaking large clock trees into multiple small ones. The principal challenge of such Globally Asynchronous Locally Synchronous (GALS) architecture is the need to communicate through the different clock domains. In this context, reliable low-cost low-latency high-throughput communication and synchronization techniques are of great interest.
Network on Chip (NoC) is advocated as a solution for the SoC interconnect problem. In NoC, numerous multiple wires, required for on-chip bit-parallel interconnect, occupy large chip area and present a significant capacitive load. We approach these challenges with high speed asynchronous on-chip serial interconnect that is the spine of this research.
The research deals with a number of communication levels:
a. Data synchronization. Different data synchronization techniques were investigated, when seeking for low-latency high-MTBF solutions. In this framework, Locally Delayed Latching (LDL) synchronization technique was developed. LDL synchronization does not require pausable clocking, is insensitive to clock tree delays, and supports high data rates.
b. NoC. Since NoC is designed to support GALS systems, it is best implemented as asynchronous circuits. In this scope, asynchronous routers for Quality-of-Service NoC were investigated. We have developed a complete asynchronous router architecture that supports multiple service levels and virtual channels.
c. Physical Link. Asynchronous SERDES link was investigated for high-rate low-power data transmission. According to our analytical study, novel serial links provide better performance than parallel links for long range communications, beyond several millimeters. We investigated low power asynchronous data transfer techniques, based on differential transition signaling. A novel bit-serial interconnect structure, comprising encoder, serializer, de-serializer, and decoder circuits, was developed and analyzed. The circuits present a lower bound on the bit time of one gate delay. The asynchronous serial link employs word-level acknowledgement, two-level data encoding (LEDR and differential), and wave-pipelining inside the serializer/de-serializer and over the communication channel. As part of asynchronous serial link investigation a novel current mode signaling technique was developed.
The results of this research enable new GALS and NoC applications, providing all critical components for full SoC integration and reducing the design cost.