|M.Sc Student||Krimer Evgeni|
|Subject||Packet-Level Static Timing Analysis for On-Chip Networks|
|Department||Department of Electrical and Computer Engineering||Supervisors||PROF. Isaac Keslassy|
|PROFESSOR EMERITUS Avinoam Kolodny|
|Full Thesis text|
Networks-on-chip (NoCs) are used in a growing number of Systems-on-Chip (SoCs) and Chip Multi Processors (CMPs), increasing the need for accurate and efficient modeling to aid the design of integrated systems. Such modeling is required for many decisions that need to be made during the design flow, such as resource allocation, placement, and QoS assurance. With no such modeling available today, the choice is limited to simulations, which are very time-consuming and often decrease the efficiency of the design.
We present a methodology for packet-level Static Timing Analysis (STA) in NoCs. It enables quick and accurate gauging of the performance parameters of a virtual-channel (VC) wormhole NoC without using simulation techniques. The network model can handle any topology, link capacities, and buffer capacities. It provides per-flow analysis that is orders-of-magnitude faster than simulation while being both significantly more accurate and more complete than prior static modeling techniques. Our methodology is inspired by models of industrial flow-lines. Using a carefully derived and reduced Markov chain, the model can statically represent the dynamic network state and closely estimate the average latency of each flow. Simulations are used to validate and evaluate the model.
As an example application, we apply our model in a placement optimization scenario. We show that our model can accurately choose between placement options to minimize end-to-end delay as verified by detailed simulation. This example also demonstrates the disadvantages and inaccuracies of prior models, which choose a sub-optimal solution over a more optimal placement.