טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
Ph.D Thesis
Ph.D StudentMorgenshtein Arkadiy
SubjectDesign and Optimization of On-Chip Interconnect
DepartmentDepartment of Electrical Engineering
Supervisors Professor Ran Ginosar
Professor Emeritus Avinoam Kolodny
Full Thesis textFull thesis text - English Version


Abstract

On-chip interconnect is a performance bottleneck of VLSI systems and is one of the major factors in power consumption. In this work I have researched and developed new design and optimization techniques for power-efficient high-performance on-chip interconnect. The research addresses both circuit-level optimization (for interconnecting logic gates and blocks) and architectural-level optimization (for links connecting Network-on-Chip routers).

Circuit-level techniques address timing optimization in logic paths with wires. Existing techniques for minimizing delay treat only the special cases of logic without wires (logical effort) or logic with a long resistive wire (repeater insertion). These particular cases are relatively rare in modern circuits. The general timing optimization problem should be based on more realistic models, which includes wires between the gates.

In this research I have developed optimization techniques addressing the fundamental questions of optimal sizing, number and location of the gates with wires. The Unified Logical Effort (ULE) method supports fast and precise optimal sizing of gates in the presence of interconnect based on intuitive closed-form expressions. The optimal number of repeaters is determined by the Gate-terminated Sized Repeater Insertion (GSRI) technique, resulting in lower delay as compared to standard repeater insertion methodologies. The Logic Gates as Repeaters (LGR) method is used for optimal wire segmenting and gate location, suggesting a distribution of logic gates over interconnect rather than using logically-redundant repeaters. The combination of these optimization methods provides solution for a wide variety of design issues.

A popular interconnect design solution at architecture level is Network-on-Chip (NoC). NoC links are used for packet-based communication among chip modules. NoC interconnect has distinctive properties such as wire sharing, low utilization and a variety of communication characteristics.

In this work I have investigated the effectiveness of serial links in NoC. A comparative analysis of serial and parallel links was performed, covering the serialization impact in terms of power, speed, area and utilization rate. I have also studied methods for power-efficient link design. The proposed techniques adapt power and speed of the link to accommodate the varying NoC communication requirements.

Solutions are proposed for power-efficient NoC links at various design levels - implementation of low-leakage repeaters, data compression using Asynchronous Bitstream Compression (ABC), and effective link utilization based on Link Division Multiplexing (LDM). This research should contribute to understanding the various aspects of NoC link design and related circuits. The proposed link design techniques and architectures should lead to more effective communications in Networks-on-Chip.