|Ph.D Student||Walter Isask'har|
|Subject||Network on Chip for Future CMP and SoC|
|Department||Department of Electrical and Computer Engineering||Supervisors||PROFESSOR EMERITUS Israel Cidon|
|PROFESSOR EMERITUS Avinoam Kolodny|
Network-on-Chip (NoC) is an emerging interconnection infrastructure offering cost-effective means for intra-chip communication. The poor scalability of buses in terms of performance and power makes them inferior to NoCs when highly integrated systems are considered. Consequently, it is widely accepted that NoCs will replace buses in future systems, though many NoC design issues are still open research questions. In this work, we address a few of these problems .
As a first contribution, we present a novel NoC architecture termed BENoC - bus-enhanced network-on-chip. BENoC is composed of a state-of-the-art NoC and an embedded, low latency bus. While the NoC is used for the delivery of high-bandwidth, point-to-point data, the bus is used for lightweight control signals that either require fast delivery or are destined at multiple destinations. We compare BENoC's energy to a conventional NoC and evaluate its performance using simulation traces.
In the second part of our research, we revisit the NoC mapping problem. We argue that future systems-on-chip will be highly regular, containing many replicated instances of task-optimized cores. In light of this observation, we extend the classic formulation of the mapping problem to account for such classes of replicated modules and for multi-stage processing pipelines. Specifically, we allow the mapping algorithm to assign data flows to the best instance within a module class. Moreover, we introduce an extended modeling of the timing requirements which captures the true application's needs. Rather than using sets of pair-wise delay requirements, we replace a "chain" of delay constraints with a single end-to-end constraint. We evaluate the benefit of the proposed techniques by comparing the cost NoCs produced by our scheme to the cost of NoCs produced by traditional mapping algorithms .
In addition, our work describes the design case-study of a NoC for a real, high-end 4G modem. Specifically, we focus on the mapping of the cores and on the optimization of link capacities that achieve the required performance. We demonstrate the importance of using the application end-to-end traversal latency requirements during the optimization process.
Finally, we introduce a novel technique for optimizing the capacities of the NoC links. Using a heuristic modeling of the delays in a wormhole NoC, the allocation algorithm predicts the communication latency on a per-flow basis and assigns individual link capacities so that the total capacity is minimized while all quality-of-service requirements are met.