|Ph.D Student||Kraus Shraga|
|Subject||Fast Delta-Sigma Analog-to-Digital Converter Based on|
|Department||Department of Electrical Engineering||Supervisor||Professor Dan Ritter|
|Full Thesis text|
Analog-to-digital converters (ADCs) based upon HBT technologies have reached record breaking sampling rates. However, the existing technologies set strict limitation on the maximum number of transistors that can be incorporated in a single circuit. As a result, HBT-based ADCs usually rely upon the flash and delta-sigma (ΔΣ) architectures.
ΔΣ ADCs consist of a feedback loop of data conversion, typically of low resolution, namely 1 to 3 bits. Nevertheless, the linearity of some of the elements embedded in the loop must be sufficiently high to support the final resolution of the ΔΣ ADC. Since digital methods of nonlinearity correction are too complex for HBT technologies, all HBT-based ΔΣ ADCs known to us incorporated a single-bit DAC, which is linear by definition. Here, we present a multibit ΔΣ ADC based upon the InP HBT technology, which incorporated an internal resolution of 2 bits.
The research consists of two stages. The first stage focused on the building blocks of the converter: a sensitivity-enhanced latched comparator, gain-enhanced amplifier, and high linearity DAC were investigated. In the second stage of the research the building blocks were put together to demonstrate a 10 GS/s second order 2-bit low pass ΔΣ ADC. Architecture, performance, stability, and other design parameters were studied.