|Ph.D Student||Bolotin Evgeny|
|Subject||Network on Chip|
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Israel Cidon|
|Professor Emeritus Avinoam Kolodny|
|Professor Ran Ginosar|
|Full Thesis text|
Rapid technology scaling in VLSI leads to increased density of VLSI System on Chips (SoCs) and Chip Multi-Processors (CMPs). As the capacity of a single die grows, more processing power and functional units can be accommodated on a single chip. On the other hand, global interconnect wires dominate the power and delay of modern VLSI systems and are becoming even more dominating over time as the technology improves. As the result, the inter-block communication becomes the main bottleneck of the system and the main problem of the design is to connect heterogeneous blocks together and to provide efficient communication infrastructure between them. Shared-bus or other ad-hoc interconnection architectures do not meet the performance requirements of modern systems and become the limiting factor that degrades performance and increases area and power costs. Therefore, new generation of interconnection networks is required for constructing scalable future VLSI systems.
In this work we focus on novel architectures of such interconnection networks for highly integrated SoCs and CMPs. Today’s interconnection systems are replaced by networked, multi-hop, packet-based communication architecture - Network on Chip (NoC). The communication protocol is completely changed and is separated from the computation tasks of the module. System modules communicate by exchanging packets over the network. In addition global ad-hoc wires currently used for signaling are eliminated and replaced by encoded packet carrying information over the network. We define Quality of Service (QoS) and cost model for communications in SoC, and derive related NoC architecture and discuss its details. We sketch the outline of future VLSI design and integration process with such NoC. We show several design examples of our NoC for typical SoC and compare to alternative solutions. We analyze the generic cost in area and power of Networks on Chip and alternative interconnect architectures. We quantify by analytical calculations the intuitive NoC scalability advantages. We also perform NoC cost optimization study, where we explore the possible cost tradeoffs between the number of buffers in network routers and the inter-router links capacity. We outline our novel, hardware-efficient methods for packet routing in irregular mesh topology, which suits the practical application-specific NoCs. Finally, we turn to NoC services and low cost mechanisms for supporting efficient shared cache access and cache coherency in future high-performance CMPs based on both static and dynamic Non Uniform Cache Architecture (NUCA) over NoC.