טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
Ph.D Thesis
Ph.D StudentPerelman Yevgeny
SubjectThe Neuroprocessor: An Integrated Interface to
Biological Neural Networks
DepartmentDepartment of Electrical Engineering
Supervisor Professor Ran Ginosar
Full Thesis textFull thesis text - English Version


Abstract

Neurons, the elementary information-processing units of the brain, represent information with bio-electrical activity. Recording this activity in neural tissues and affecting it by means of electrical stimulation is the dominant method of neurophysiological research. Clinical applications of that research include treatment of neural diseases, restoration of lost sensory functions, and limb prostheses: artificial limbs directly controlled by signals from patient's motor cortex.


Electrode arrays for neural recording with hundreds of sensing sites are available; indications exist thousands of channels are necessary for fine limb control. Stringent requirements are posed on the equipment used for neuronal interfacing when considering wireless implantable devices with high channel counts. Concepts used in existing equipment are based mostly on discrete-components, connected with wire bundles to signal acquisition.


This research investigates VLSI circuits and architectures for neural interfacing, both in-vivo (interfacing tissues in live animals) and in-vitro (interfacing cultured or dissected tissues on a special dish). The main contribution of this work is the introduction of the concept of Neuroprocessor, a computational neuronal interface. Unlike traditional neuronal interfaces, the Neurprocessor exploits the large integration possibilities offered by VLSI technology: It performs significant amounts of computation right at the recording/stimulation frontend, rather than mere transduction of neuronal signals/stimuli. The computation capabilities can be used to pre-process the recorded signals, extract the relevant features and communicate only those features, saving communication bandwidth and enabling low-power wireless operation. It is shown that applying low-level neural signal analysis, common to most neurological experiments (i.e. detection and sorting of neuronal firing), can save up to 99% of communication bandwidth required at the frontend. The computation is also necessary when autonomous operation of implanted devices is considered.


The research was conducted in three directions. Novel circuits were designed towards VLSI implementation of the Neuroprocessor: Three generations of integrated circuits, NPR01-NPR03, were designed and tested. Neurophysiological experiments were successfully conducted with NPR03. An effort was made in the research of data reduction algorithms suitable for low-power VLSI implementation. Existing algorithms for neural signal analysis were modified, trading computation precision for complexity savings.


Yet another effort was made in developing a silicon replacement for the (glass) dish for in-vitro growth and interfacing of neural tissues. An integrated circuit for neural culturing and recording was developed, using only a standard-CMOS process, with no proprietary post-processing steps involved. Neurons were cultured on this circuit with their activity successfully measured.