|M.Sc Student||Dobkin Rostislav|
|Subject||Parallel VLSI Architecture and Parallel Interleaver|
Design for MAP Turbo Decoder
|Department||Department of Electrical Engineering||Supervisors||Professor Ran Ginosar|
|Mr. Michael Polacek|
Standard VLSI implementation of turbo decoding requires substantial memory and incurs a long latency, which cannot be tolerated in some applications. A novel parallel VLSI architecture for low-latency turbo decoding was developed, comprising multiple SISO elements, operating jointly on one turbo coded block, and a new parallel interleaver. The design algorithm for the parallel interleaver was developed, enhancing the error correction performance of the parallel architecture.
The parallel interleaver design algorithm has fast convergence characteristics and matches the performance of the most advanced published interleavers for the sequential case. The algorithm may be used to design high-performance interleavers for the standard sequential architectures.
A significant linear reduction of latency was achieved (up to a factor of 20) in comparison with a sequential turbo decoder. In addition, it was found that for large blocks the parallel architecture is more area efficient, improving throughput up to a factor of 5 for the same chip. The power consumption was found to be equal to that of the sequential decoder for the same throughput requirement. The error correction performance was within 0.05 dB of that of the sequential turbo decoder.
The parallel architecture and the parallel interleaver design algorithm achieved an attractive cost/performance ratio and an attractive performance in terms of BER, latency and throughput.