|M.Sc Student||Gurevich Alexey|
|Subject||Developing a 3-D Layout for Wafer Fabrication Plants|
|Department||Department of Industrial Engineering and Management||Supervisor||Professor Boaz Golany|
Designing plant layout is a complicated and important issue, which has a major impact on the plant’s future performance. A common method for determining a plant layout is by placing the production machines or departments so as to minimize the total material handling costs. This problem has been formulated as a Quadratic Assignment Problem (QAP), which is known as NP-Hard problem. Therefore, different heuristics were developed.
Most production systems are arranged on a 2D plane in a single floor. This structure complicates various issues concerning material handling, especially in an Automated Material Handling environment.
In contrast to the common practice in production floors, Automated Storage/Retrieval Systems (AS/RS) work in a 3D space, organized by aisles, which are served by AGV. The AGVs move in the aisles from the I/O point to a cell for storage assignment and from a cell back to the I/O point for retrieval.
This research offers a 3D layout for general production floors and tests its feasibility for a semiconductors industry. The research uses various methods that were customized for 3D layout environment: optimization models that analyze different cost aspects, heuristics models (e.g., simulated annealing) and simulation models that were developed using the ARENA software package to analyze various performance measures. A real-world semiconductors production process is analyzed using large-scale simulation model developed for the research.
The research concludes that the 3D layout is potentially valuable for reducing material handling costs, work in process levels and throughput times.