M.Sc Thesis | |

M.Sc Student | Michaely Shay |
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Subject | Wire Resizing for Optimal Migration of Microprocessors |

Department | Department of Electrical and Computer Engineering |

Supervisors | ASSOCIATE PROF. Shmuel Wimer |

PROFESSOR EMERITUS Avinoam Kolodny |

The problem of simultaneously allocating wire widths and spaces to all wires in parallel bus structures under a total area constraint, for circuit performance optimization, is presented. This problem is significant in the context of microprocessors layout migration process, where area is a major design constraint. When an existing layout is being migrated, the wires delays have increasing effect on circuit timing, because wire resistance and cross capacitances do not scale well. Hence, there is a need for careful sizing and spacing of wires.

Four objective functions are defined for solving the sizing optimization problem under the area constraint: total sum of delays or slacks, and MinMax of delays or slacks. Different characteristics of the objective functions, such as convexity, necessary and sufficient conditions for optimum, are proven. The optimal solution of the MinMax problem is bounded by the solution of the corresponding total sum of delays problem. An iterative algorithm for finding the optimal bus layout is constructed, based on the necessary and sufficient conditions. Solution examples are presented. Design implications are derived and discussed.

At the initial stages of layout migration the sum of all signals delays is a good target for minimization. At the final design stages, tuning to minimize the maximal wire delay in the bus should be performed. When required arrival times are known for the signals, the bus can be optimized for maximal average slack, or tuned for maximal slack in the most critical signal.