|M.Sc Student||Zviagintsev Alex|
|Subject||Hardware Algorithms and Architectures for Power Spike|
Detection and Sorting
|Department||Department of Electrical Engineering||Supervisor||Professor Ran Ginosar|
Front-end integrated circuits for signal processing are useful in neuronal recording systems that engage a large number of electrodes. Detection, alignment, and sorting of the spike data at the front-end reduces the data bandwidth and enables wireless communication. We explore Neuroprocessor electronic chips for portable applications. The Neuroprocessor can be placed next to the recording electrodes and provide for all stages of spike processing, stimulating neuronal tissues and wireless communication to a host computer. It can dissipate only a limited amount of power, due to supply constraints and heat restrictions.
We introduce hardware algorithms and architectures for automatic spike detection and sorting in Neuroprocessors, designed to reduce data rates. The proposed architectures are applied on pre-recorded neuronal data and compared in terms of computational complexity and sorting error. Some of the algorithms compare the spike with predetermined values in time domain. Others employ a novel Integral Transform analysis and achieve 98% of the precision of a PCA sorter, while requiring only 2.5% of the complexity. The algorithms execute autonomously, but require off-line training and setting of parameters. We concluded that time-domain classification is simple to implement and incurs low complexity, however it results in high error rates. Detection and sorting in the analog domain deserve special attention thanks to their simplicity and high performance. The Integral Transform efficiently lowers the dimension and reduces power consumption, while emphasizing the differences among spike types. Thus, we have selected this method for power efficient spike detection and sorting in a multi-electrode integrated circuit for neuronal processing