הטכניון מכון טכנולוגי לישראלXyz
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים 
Ph.D and MS.c Theses, since 1988.


Advisor Professor Emeritus Avinoam Kolodny
Advisor's Email kolodny@ee.technion.ac.il
Advisor's Home-Site www
No of theses 44
Department Electrical Engineering
Department Web Site webee.technion.ac.il/hebrew


No.   Student's Name Graduation
Year
Degree Abstracts Research Name
 1 Levy Yifat 2016 MSc Abstracts Digital Circuits Design Using Memristors
 2 Morad Tomer 2016 PhD Abstracts Energy- Efficient System Resource Allocation
 3 Zahavi Eitan 2016 PhD Abstracts Forwarding in Computer Cluster Networks
 4 Ben-Itzhak Yaniv 2014 PhD Abstracts Advanced Heterogeneous NoC Design
 5 Kvatinsky Shahar 2014 PhD Abstracts Memristor-Based Circuits and Architectures
 6 Manevich Ran 2014 PhD Abstracts Centralized Paradigms in Network on Chip Architectures
 7 Stanislavsky Amnon 2013 MSc Abstracts Power Driven Floorplan and Energy Efficient Adders
 8 Polishuk Leon 2013 MSc Abstracts Latency considerations for NoC interconnection fabrics
 9 Izchak Oved 2013 MSc Abstracts The Interaction between Workloads and Micro Architecture in Highly-Parallel Chip Multi-Processors
 10 Cohen Yaron 2012 MSc Abstracts Low Power D/A Converter Design Considerations
 11 Abdelhadi Ameer 2011 MSc Abstracts Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks
 12 Malits Roman 2011 MSc Abstracts The Potential of Global Scheduling to Improve Utilization in Wide SIMD GPGPU Architectures
 13 Sizikov Gregory 2011 MSc Abstracts Design and Analysis of integrated voltage regulators
 14 Vishnyakov Victorya 2011 MSc Abstracts Inductive Effects in On-Chip Interconnects
 15 Moiseev Konstantin 2011 PhD Abstracts Optimization of Interconnects in CMOS Nanoscale Technologies
 16 Ben-Itzhak Yaniv 2010 MSc Abstracts Performance and Power Aware Thread Allocation for NoC CMP
 17 Damishian Chen 2010 MSc Abstracts Stride Based Dead Block Correlation Prefetcher - A New Long-Latency-Tolerant Data Cache Prefetcher
 18 Zobel Shmuel 2010 MSc Abstracts Power Performance Tradeoffs in Graphics/GPGPU Based Systems
 19 Guz Zvika 2010 PhD
The Interplay of Caches and Threads in Chip-Multiprocessors
 20 Kouslik Elkin Anna 2010 MSc Abstracts Macro Models for Power Estimation at RT Level in VLSI
 21 Walter Isask'har 2010 PhD Abstracts Network on Chip for Future CMP and SoC
 22 Aizik Yoni 2009 MSc Abstracts Design Considerations for Low Power CMOS Digital Circuits
 23 Krimer Evgeni 2009 MSc Abstracts Packet-Level Static Timing Analysis for On-Chip Networks
 24 Vaisband Inna 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction
 25 Dobkin Rostislav 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC
 26 Barash Dror 2008 MSc Abstracts Cache Manipulations Improve Multimedia Applications
 27 Sorani Iris 2008 MSc Abstracts Long Instruction Traces and their Usage
 28 Morgenshtein Arkadiy 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect
 29 Sotman Michael 2007 MSc Abstracts Issues in Analysis and Design of Power Delivery Structures in VLSI
 30 Bolotin Evgeny 2007 PhD Abstracts Network on Chip
 31 Behar Michael 2006 MSc Abstracts Characterization of Hot Traces in Modern Processors
 32 Walter Isask'har 2006 MSc Abstracts Quality of Service in Network on-Chip
 33 Kapchits Anastasia 2006 MSc Abstracts Modeling and Design of Network on Chip Interconnects
 34 Morad Tomer 2005 MSc Abstracts Data Trace Cache
 35 Moiseev Konstantin 2005 MSc Abstracts Performance Optimization by Reordering of Interconnect Wires in VLSI
 36 Michaely Shay 2005 MSc Abstracts Wire Resizing for Optimal Migration of Microprocessors
 37 Moreinis Michael 2004 MSc Abstracts Repeater Insertion in Deep Sub-Micron VLSI Circuits
 38 Magen Nir 2004 MSc Abstracts Power Issues of On-Chip Interconnect in VLSI
 39 Khamaisee Assad 2004 MSc Abstracts Combining Trace Cache with Value Prediction in Microprocessors
 40 Milter Oleg 2002 MSc Abstracts Synthesis of CMOS VLSI Circuits Considering Digital Noise Effects
 41 Shchupak George 2002 MSc Abstracts High Speed, Low Power Medium Size Cache Design
 42 Kosyakovsky Oleg 2002 MSc Abstracts Approaches to Managing Trace Cache in Computer Systems
 43 Elboim Yaron 2002 MSc
A Clock Tuning Circuit for System-on-Chip
 44 Dolev Noam 2002 MSc Abstracts Integrated Low-Voltage Delta-Sigma Conversion Circuits in Digital CMOS Technology

Last updated on: Friday ,August 16, 2019