Ph.D and MS.c Theses, since 1988. Advisor Assoc. Prof. Kolodny Avinoam Advisor's Email kolodny@ee.technion.ac.il Advisor's Home-Site  www No of theses 35 Department Electrical Engineering Department Web Site webee.technion.ac.il/hebrew No. Student's Name Graduation Year Degree Abstracts ResearchName 1 Yaron Cohen 2012 MSc Abstracts Low Power D/A Converter Design Considerations 2 Konstantin Moiseev 2011 PhD Abstracts Optimization of Interconnects in CMOS Nanoscale Technologies 3 Roman Malits 2011 MSc Abstracts The Potential of Global Scheduling to Improve Utilization in Wide SIMD GPGPU Architectures 4 Ameer Abdelhadi 2011 MSc Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks 5 Victorya Vishnyakov 2011 MSc Abstracts Inductive Effects in On-Chip Interconnects 6 Gregory Sizikov 2011 MSc Abstracts Design and Analysis of integrated voltage regulators 7 Isask'har Walter 2010 PhD Abstracts Network on Chip for Future CMP and SoC 8 Zvika Guz 2010 PhD Abstracts The Interplay of Caches and Threads in Chip-Multiprocessors 9 Yaniv Ben-Itzhak 2010 MSc Abstracts Performance and Power Aware Thread Allocation for NoC CMP 10 Anna Kouslik Elkin 2010 MSc Abstracts Macro Models for Power Estimation at RT Level in VLSI 11 Chen Damishian 2010 MSc Abstracts Stride Based Dead Block Correlation Prefetcher - A New Long-Latency-Tolerant Data Cache Prefetcher 12 Shmuel Zobel 2010 MSc Abstracts Power Performance Tradeoffs in Graphics/GPGPU Based Systems 13 Rostislav Dobkin 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC 14 Yoni Aizik 2009 MSc Abstracts Design Considerations for Low Power CMOS Digital Circuits 15 Evgeni Krimer 2009 MSc Abstracts Packet-Level Static Timing Analysis for On-Chip Networks 16 Inna Vaisband 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction 17 Arkadiy Morgenshtein 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect 18 Iris Sorani 2008 MSc Abstracts Long Instruction Traces and their Usage 19 Dror Barash 2008 MSc Abstracts Cache Manipulations Improve Multimedia Applications 20 Evgeny Bolotin 2007 PhD Abstracts Network on Chip 21 Michael Sotman 2007 MSc Abstracts Issues in Analysis and Design of Power Delivery Structures in VLSI 22 Isask'har Walter 2006 MSc Abstracts Quality of Service in Network on-Chip 23 Michael Behar 2006 MSc Abstracts Characterization of Hot Traces in Modern Processors 24 Anastasia Barger 2006 MSc Abstracts Modeling and Design of Network on Chip Interconnects 25 Tomer Morad 2005 MSc Abstracts Data Trace Cache 26 Shay Michaely 2005 MSc Abstracts Wire Resizing for Optimal Migration of Microprocessors 27 Konstantin Moiseev 2005 MSc Abstracts Performance Optimization by Reordering of Interconnect Wires in VLSI 28 Nir Magen 2004 MSc Abstracts Power Issues of On-Chip Interconnect in VLSI 29 Assad Khamaisee 2004 MSc Abstracts Combining Trace Cache with Value Prediction in Microprocessors 30 Michael Moreinis 2004 MSc Abstracts Repeater Insertion in Deep Sub-Micron VLSI Circuits 31 George Shchupak 2002 MSc Abstracts High Speed, Low Power Medium Size Cache Design 32 Oleg Kosyakovsky 2002 MSc Abstracts Approaches to Managing Trace Cache in Computer Systems 33 Oleg Milter 2002 MSc Abstracts Synthesis of CMOS VLSI Circuits Considering Digital Noise Effects 34 Yaron Elboim 2002 MSc A Clock Tuning Circuit for System-on-Chip 35 Noam Dolev 2002 MSc Abstracts Integrated Low-Voltage Delta-Sigma Conversion Circuits in Digital CMOS Technology Last updated on: Tuesday ,May 14, 2013