Ph.D and MS.c Theses, since 1988. Advisor Assoc. Prof. Ginosar Ran Advisor's Email ran@ee.technion.ac.il Advisor's Home-Site  www No of theses 49 Department Electrical Engineering Department Web Site webee.technion.ac.il/hebrew No. Student's Name Graduation Year Degree Abstracts ResearchName 1 Shimon Manor 2013 MSc Abstracts Multi-Synchronous Clocking for Low Power 2 Eyal-Itzhak Nave 2012 MSc Abstracts TCP Window Based Dynamic Voltage and Frequency Scaling (DVFS) for Low Power Communication Network Controller System on Chip (SoC) 3 Yaron Cohen 2012 MSc Abstracts Low Power D/A Converter Design Considerations 4 Itai Avron 2012 MSc Abstracts Scheduler Performance in Many-core Architecture 5 Eyal Friedman 2011 MSc Abstracts Processor-to-Memory Non-Equidistant Network in a Many-Core Architecture 6 Ameer Abdelhadi 2011 MSc Timing-Driven Variation-Aware Synthesis of Hybrid Mesh/ Tree Clock Distribution Networks 7 Dmitri Khoretz 2011 MSc Abstracts Cores and Memory Performance of HyperCorex: Many-Core Architecture 8 Dmitri Vainbrand 2010 MSc Abstracts Network-on-Chip Architecture for Neural Networks 9 Rostislav Dobkin 2009 PhD Abstracts High-Speed Asynchronous Communication for SoC 10 Inna Vaisband 2009 MSc Abstracts Power Efficient Tree-Based Crosslinks for Skew Reduction 11 Arkadiy Morgenshtein 2008 PhD Abstracts Design and Optimization of On-Chip Interconnect 12 Asaf Baron 2008 MSc Abstracts The Capacity Allocation Paradox 13 Evgeny Bolotin 2007 PhD Abstracts Network on Chip 14 Yevgeny Perelman 2007 PhD Abstracts The Neuroprocessor: An Integrated Interface to Biological Neural Networks 15 Ziv Yekutieli 2007 MSc Abstracts Integrated Multi-Electrode Array: An Interface to Ex Vivo Neural Networks 16 Michael Kayam 2007 MSc Abstracts Synchronizers for Low Voltage and Low temerature Operation 17 Avshalom Elyada 2007 MSc Abstracts Low-Complexity Policies for Energy-Performance Tradeoff in Chip-Multi-Processors 18 Michael Tolchinsky 2007 MSc Abstracts Implementation of New Method of Measurement for Metastability Coefficient for Flip-flops 19 Yitschak Kapschitz 2006 MSc Abstracts Formal verification of synchronizers 20 Isask'har Walter 2006 MSc Abstracts Quality of Service in Network on-Chip 21 Alexander Lyakhov 2006 MSc VLSI Sensor Chip for In-Vitro Measurement of Biological Neural Network Activity 22 Uri Frank 2005 MSc Abstracts A Predictive Synchronizer for Bridging Different Frequency Clock Domains 23 Alex Zviagintsev 2005 MSc Abstracts Hardware Algorithms and Architectures for Power Spike Detection and Sorting 24 Ilya Obridko 2005 MSc Abstracts Minimal Energy Asynchronous Adder Architectures 25 Guy Tamir 2004 MSc Abstracts Synchronizers Metastability 26 Rostislav Dobkin 2003 MSc Abstracts Parallel VLSI Architecture and Parallel Interleaver Design for MAP Turbo Decoder 27 Yaron Semiat 2003 MSc Abstracts Design, Implementation and Test of Adaptive Synchronization Circuits 28 Sagi Katz 2003 MSc Abstracts Polyhedral Surface Decomposition and Applications 29 Yaron Elboim 2002 MSc A Clock Tuning Circuit for System-on-Chip 30 Yevgeny Perelman 2001 MSc A Low-Light Sensor for Medical Diagnostic Applications 31 Boris Shpolyansky 1999 MSc Improving of Performance of Superscalar Microprocessors Using Scheduling History 32 Rakefet Kol 1998 PhD Self-Timed Asynchronous Architecture of an Advanced General Purpose Microprocessor 33 Hod Finkelstein 1998 MSc Frontside-Bombarded Metal-Plated Electron Radiation Imaging Chip Fabricated in Cmos Technology 34 Marina Sherman 1997 MSc Intelligent-Scan Based Transmission and Retrieval of Images 35 Amir Freizeit 1995 MSc Hierarchical Conditional Replenishment Video Compression Algorithm and Architecture 36 Sarit Chen-Levy 1995 MSc Adaptive Sensitivity Ccd Image Sensor 37 Leonid Yavits 1995 MSc Architecture and Design of An Associative Processor Chip 38 Nitzan Weinberg 1995 MSc A Neural Network Architecture for Image Processing 39 Arie Harsat 1993 PhD Llsi Architectures for Flat Concurrent Prolog 40 Stuart Wolf 1992 MSc Development of a Colour Enhancealgorithm Using Spatial Proce 41 Shimon Gur 1990 MSc Design of Carmel 2 and Its Implementation with Silicon 42 Orly Yadid-Pecht 1990 MSc An Lmaging System with Random Access 43 Abraham Nathan 1989 MSc Compilation of Fcp to Carmel and Its Performance Analysis 44 Aviad Mintz 1989 MSc Design of Vlsi Prolessor for Hough Transform 45 Alan Rotman 1989 MSc Control Unit Syntesis from a High Level Language 46 Rakefet Kol 1989 MSc Self-Timed Finite-State Machines 47 Baruch-Ram Friedlander 1989 MSc Vlsi Architecture for Morphological Operations 48 Dov Alon 1989 MSc Switch Controller for Mp/l Parallel Processor 49 Ricardo Telichevesky 1988 MSc A Vlsi Architecture for Fntelligent Scan Image Processing Last updated on: Wednesday ,May 22, 2013