טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
Ph.D Thesis
Ph.D StudentHemo Evyatar
SubjectAlgorithms and Coding Schemes for Enhanced Performance
and Reliability in Multi-Level Non-Volatile
Memories
DepartmentDepartment of Electrical Engineering
Supervisor Professor Yuval Cassuto
Full Thesis textFull thesis text - English Version


Abstract

Solid-state storage technologies, most prominently flash memories, constantly grow in their storage densities and become the most attractive media for many applications. One way in which improved density is achieved is by increasing the number of levels to which a cell can be programmed. Commercial 8-level (3b/cell) flash memories are already widely used, while researchers are pursuing devices with as high as 64 memory levels. However, using more levels per cell also increases the time needed for reading and writing the data, thereby introducing tradeoffs between storage density and access speed. This is because more levels mean longer processes to accurately set the cell levels upon write, and to measure them with precision upon read. In addition, the reliability of the memory is significantly compromised due to solid-state effects changing a cell's stored level. The main purpose of the research in this thesis is to enhance the performance of multi-level non-volatile memories (NVMs). Performance enhancement is achieved by both speeding up read and write processes and by improving the reliability of the media. In order to enhance read and write performance, we use two primary schemes. The first scheme includes a set of adaptive read algorithms on memory words and arrays, in which the read process is adaptively changing as a function of the outcome of the read process so far. The second scheme is a coding scheme in which the stored codewords induce faster write and read processes. Reliability improvement is achieved by two new coding schemes. The first is an error-correcting scheme which includes a constraint designed to correct asymmetric magnitude-1 errors which are common in multi-level NVMs. The second proposes write-once (WOM) codes that reduce inter-cell interference (ICI). WOM codes enable to perform multiple writes without erasing the media, so by using WOM codes in multi-level NVMs it is possible to reduce the wear of the media and extend the lifetime of the device. The new proposed WOM model addresses the ICI problem within the WOM framework, and our work shows constructively how WOM codes can simultaneously reduce ICI and offer many writes between physical erases