טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentFarber Aryeh
SubjectDesign and Analysis of High Performance Time to Digital
Converters
DepartmentDepartment of Electrical Engineering
Supervisor Assistant Professor Emmanuel Cohen
Full Thesis textFull thesis text - English Version


Abstract

In many modern RF design applications there is an increasing demand for Time to
Digital Converters (TDCs) which combine a sub pico second resolution, a dynamic
range of several hundreds of pico seconds, and an acceptable power consumption. State of the art TDC’s typically support either a large dynamic range or high resolution - not both combined.

Flash TDC’s (FTDC’s) can support measurement of a large dynamic range by increasing the number of its stages but its resolution is limited to several pico seconds. Interpolating delay chains, Vernire structures, cyclic TDC’s and other techniques can be applied to improve the resolution of a FTDC. However, these techniques are limited by flip flop mismatch and entail a high power consumption.

Stochastic TDCs (STDC) on the other hand are a well-established technique to enable fine resolution but are limited to a dynamic range of ±3s of the setup time of a latch, i.e. ~12ps in a modern technology.

The main innovation of this thesis is the development and implementation of a Stochastic Flash TDC (SF-TDC) which combines a FTDC with the STDC concept to achieve high resolution. A SF-TDC is a tapped delay chain flash TDC with a Stochastic TDC on each of its taps. The SF-TDC concept has been reported, however the increased number of latches on each of the delay chain taps make such a TDC extremely aggressive and power hungry and thus implementations are not reported. This thesis presents an implementation which achieves a resolution of ~0.4ps resolution while supporting a wide dynamic range of 400 pico seconds.

It is technically challenging to keep power consumption of such an architecture down to an acceptable level.  Typical state of the art TDCs driven by GHz signals consume about 5-20 mA, depending on resolution and architecture. In the implementation of this thesis achieved current consumption is 5 mA, which is low given the high TDC resolution.