טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
M.Sc Thesis
M.Sc StudentOron Port
SubjectCAFEO: A Dataflow, Device-Agnostic, Synthesizable Hardware
Description Language
DepartmentDepartment of Electrical Engineering
Supervisor Professor Etsion Yoav
Full Thesis textFull thesis text - English Version


Abstract

Java's "Write Once, Run Anywhere" concept for field-programmable gate array (FPGA) devices has not eluded the electronic design automation (EDA) industry. As hardware designs and FPGA architectures became increasingly more complex, utilizing traditional hardware-description languages (HDLs) like VHDL and Verilog resulted in a verbose and non-portable code, tightly coupled to a specific device and timing requirements. In an effort to raise the level of abstraction, several high-level synthesis (HLS) tools and languages were introduced, but none have yet to become mainstream. 


In this research we explore the main fallacies behind modern HDLs. We then present Constructible for Any FPGA, Expressed Once (CAFEO) HDL and compiler - a new Scala-based HLS tool. CAFEO's front-end enables functional bit accurate dataflow programming, while maintaining a complete timing-agnostic and device-agnostic code. CAFEO bridges the gap between software programming and hardware construction, driving an intuitive functional object oriented code into a high performance hardware implementation.


We have evaluated the CAFEO language and compiler by implementing an Advanced Encryption Standard (AES) cipher block and an IEEE-754 floating point multiplier. We compare both test cases against current design flows with VHDL/Verilog. Our results demonstrate competing performance while simplifying code verbosity significantly.