טכניון מכון טכנולוגי לישראל
הטכניון מכון טכנולוגי לישראל - בית הספר ללימודי מוסמכים  
Ph.D Thesis
Ph.D StudentRoy Winter
SubjectThe Role of Interfaces and Defects in Controlling the
Properties of InGaAs MOS Devices
DepartmentDepartment of Materials Science and Engineering
Supervisor Professor Emeritus Eizenberg Moshe
Full Thesis textFull thesis text - English Version


Abstract

The continuous scaling of microelectronic devices demands integration of new materials for future devices. InGaAs is a leading candidate to serve as the channel material of future transistors due to its high carrier mobility with respect to Si. However, replacing Si with InGaAs leads to new challenges, stemming from a lower interface quality. The experience from Si Metal-Oxide-Semiconductor (MOS) stacks research has established the conclusion that there is a tight connection and complex interaction between all the gate stack components, emphasizing the importance of studying the properties of the gate stack as a whole.

The objective of this research was to determine the role of interfaces and defects in controlling the properties of MOS devices consisting of a metal electrode, a high dielectric constant (high-k) oxide, and InGaAs as a high-mobility substrate. In particular, interest was focused on the effect of metallization on the electrical properties of these devices, and their correlation with the composition and band structure of the high-k/semiconductor interface. We have used electrical characterization methods combined with high-resolution transmission electron microscopy, time of flight secondary ion mass spectrometry, and x-ray photoelectron spectroscopy in to achieve the research goals.

At the first stage, we have developed a new method for determining the flat-band voltage in high mobility semiconductors, insensitive to the high density of interface traps typical of these materials. By using this new method, we have correlated Fermi level pinning with the materials constituting the gate stack, the metal deposition methods, and various processing steps such as post-oxide and post-metal deposition annealing. We have examined the effects of the type of the gate metal used and its deposition method on the presence of point defects in the gate stacks and on the chemical stability of key interfaces.

We have demonstrated the effect of oxides scavenging on the interface trap in high-k/InGaAs interface by using a Ti thin layer. The scavenging of InGaAs native oxides in Ti/high-k/InGaAs gate stack was investigated using electrical measurements and XPS analysis.

Finally, we have studied the degradation of the Al2O3/InGaAs interface by the investigation of metal gate/Al2O3/InGaAs stacks under constant voltage.

In Si MOSFETs due to the high quality SiO2/Si interface, the main focus was on the upper interface, the metal/dielectric interface. The metal gate was chosen by fitting the metal work function with the work function of the semiconductor and by the metal chemical stability with the dielectric layer. In contrast, previous studies have shown that the main focus in InGaAs based MOSFETs is on the lower interface, the dielectric/InGaAs interface. Many efforts have been made to improve this interface thus improving the performance of the device. In this study we have shown for the first time that the metal choice can affect not only the upper interface but also the lower interface. The phenomena presented in this work are important and must be taken into account in designing the future InGaAs based MOSFETs.