|M.Sc Student||Oz Nitzan|
|Subject||Millimeter Wave Frequency Source Circuits in 28nm|
CMOS Process for Phased Array Systems
|Department||Department of Electrical Engineering||Supervisor||Assistant Professor Emmanuel Cohen|
|Full Thesis text|
The increasing demand of high data rate communication systems for applications such as: imaging, security, remote sensing etc', lead to a vast research of circuits in the millimeter wave spectrum in recent years - especially for CMOS. The need for efficient and small size frequency sources emerged as an important building block in these systems using multiple phased array chains in order to overcome the high atmospheric loss. Analysis of voltage-controlled oscillator (VCO) revealed that VCO suffers from high phase noise, narrow tuning range, and a non-flat output power at high frequencies. In order to overcome these performance issues, a multiplier topology is the best choice. In this research we focused first on a doubler design above 100 GHz. The doubler performance was derived mathematically based on a short channel simplified model. Two doubler topologies were compared in simulation, single ended vs. balanced (Push-Push), founding that Push -Push topology is 1-2 dB better in output power as a result of low output loss. The doubler final design was implemented under balanced topology for optimal size and power. A novel input network was implemented enabling single ended to differential transformation and second harmonic short in very compact form. The input network together with the new simulation methodology (harmonic source pull) resulted in more than 40% power reduction and 1/3 in size compared to the state of the art doublers. The doubler was designed for F-band frequencies, covering 105-130 GHz and fabricated in 28nm CMOS. A peak output power of dBm with 18% efficiency and .8 dBm with 14% efficiency at 120 GHz for 19μm and 32μm doubler core sizes were achieved, occupying 0.03mm2 each. The 32um core size doubler was integrated with a transceiver for mmW chip to chip communication system.
In the second phase of the research a VCO with sub harmonic injection lock (SHIL) mechanism was also analyzed and fabricated. The purpose was to create a pre-multiplication frequency system for the mmW doubler. The state of the art SHIL VCO circuits today show low frequency multiplication ratio N ≤ 8 with high power consumption. Our SHIL VCO was designed for frequency multiplication ratio of N>10 while maintaining high efficiency. The VCO was implemented with single ended /differential injection, controlled over pulse width and pulse delay. By simulation, an optimal injected signal pulse width was found (approximately 20ps). Special digital logic circuit was designed to balance the differential paths and enable short pulse generation. The SHIL VCO was designed for the K-Band spectrum and taped out in 28nm CMOS. Frequency multiplication ratio of N=11 with power consumption of 4mW were achieved, that is the lowest power consumption for such high harmonic ratio known to the authors. Moreover, the injected spurs levels were 40dB down thanks to the differential topology. The chip occupies a size of 0.64 mm2. Future work is required for improving the gain of the VCO to wake up without injection and increase the SHIL VCO frequency to 60GHz to fit the doubler frequency.