|M.Sc Student||Tomer Saraf|
|Subject||Study of CMOS-SOI Readout Circuits for Uncooled|
Infra-Red TMOS Sensors
|Department||Department of Electrical Engineering||Supervisors||Professor Emeritus Nemirovsky Yael|
|Dr. Unikovski Aharon|
|Full Thesis text|
Recent progresses in implementing uncooled infrared sensors in CMOS - SOI (silicon on isolator) - NEMS (nano electro mechanical systems) technology, offer the opportunity to achieve highly integrated cost-effective System-on-Chip (SoC) sensors for a wide range of infrared applications. This research focuses on the design of monolithically integrated electronic system, formed by the infrared sensor, its front-end analog interface and the processing circuitry.
The Technion’s TMOS thermal sensor that has been developed in the CMOS-SOI-NEMS technology, opened new opportunities for mass-produced consumer applications needing high performance thermal sensing (noise equivalent temperatures of less than 1°K) at potentially a fraction of the cost, compared to currently available high performance thermal sensors (such as the micro-bolometers). The CMOS-SOI-NEMS technology is extremely established and relatively low-cost for high production volumes. Combining the entire sensing system that includes the sensor, analog readout circuits and a digital processing core, further enhances the potential performance of the system since the readout can be optimally designed to match the TMOS sensor.
In this work, research of the sensor and the readout circuits was performed by implementing an intruder sensor (motion detector) system. First, the TMOS sensor was analyzed and modeled in both the thermodynamic and the electrical domains, and the approach of voltage- and current-modes interface was introduced. Then, an array of TMOS pixels operating in the sub-threshold region was designed and optimized to provide high signal-to-noise ratio while maintaining very low power consumption. To match the low-noise and low-power requirements, different front-end analog readout topologies were studied, and the instrumentational amplifier configuration was chosen for its high input impedance that eases interfacing with a voltage-mode TMOS array. Lastly, a calibration circuit was designed to mitigate for process mismatches impact on system offsets.
Two test chips were manufactured in STM 0.13um SOI process, one for measuring different TMOS arrays and another for characterizing the analog circuitry. Both chips are showing high level of functionality and performance, enabling the next step of integrating them into one SoC.